HYB39S13620TQ-6

www.DataSheet4U.com Overview HYB 39S13620TQ-6/-7/-8 High Performance: -6 -7 125 2 8 5.5 -7 125 3 7 5.5 -8 125 3 8 6 Units MHz − ns ns Special Mode Registers Two color registers Burst Read with Single Write Operation Block Write and Write-per-Bit Capability Byte controlled by DQM0-3 Auto Precharge and Auto Refresh Modes Suspend Mode and Power Down Mode 2k refresh cycles/32 ms tAC = 5 ns tSETUP/tHOLD = 2 ns/1 ns Latency 2 @ 125 MHz Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL compatible inputs and outputs fCK latency 166 3 6 5.5 tCK3 tAC3 Single Pulsed RAS Interface Programmable CAS Latency: 2, 3 Fully Synchronous to Positive Clock Edge Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page for sequential 1, 2, 4, 8 for interleave The HYB 39S163200TQ are dual bank Synchronous Graphics DRAM’s (SGRAM) organized as 2 banks × 256 Kbit × 32 with built-in graphics features. These synchronous devices achieve high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with an advanced 64MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous graphics DRAM products, both electrically and mechanically. RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the posit...