GS8640ZV18T

Product Preview GS8640ZV18/36T-300/250/200/167 www.DataSheet4U.com 100-Pin TQFP Commercial Temp Industrial Temp Features NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs 1.8 V +10%/–10% core power supply 1.8 V I/O supply User-configurable Pipeline and Flow Through mode LBO pin for Linear or Interleave Burst mode Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices Byte write operation (9-bit Bytes) 3 chip enable signals for easy depth expansion ZZ Pin for automatic power-down JEDEC-standard 100-lead TQFP package Pb-Free 100-lead TQFP package available 72Mb Pipelined and Flow Through Synchronous NBT SRAM 300 MHz–167 MHz 1.8 V VDD 1.8 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8640ZV18/36T may be configured by the user to o...