Document
Ordering number : EN3586A
CMOS LSI
LC7574NE, 7574NW
1/2 Duty VFD Driver for Frequency Display
Overview
The LC7574NE and LC7574NW are 1/2 duty VFD drivers that can be used for electronic tuning frequency display and other applications under the control of a controller. These products can directly drive VFDs with up to 74 segments.
Package Dimensions
unit: mm 3156-QFP48E
[LC7574NE]
Features
• 74 segment outputs • Noise reduction circuits are built into the output drivers. • Serial data input supports CCB* format communications with the system controller. • Switching between digital and analog dimmers under serial data control • High generality since display data is displayed without the intervention of a decoder • All segments can be turned off with the BLK pin
SANYO: QFP48E • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.
unit: mm 3163A-SQFP48
[LC7574NW]
SANYO: SQFP48
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O2095HA (OT)/4032JN No. 3586-1/10
LC7574NE, 7574NW
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VFL max VIN1 VIN2 VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg VDD VFL DI, CL, CE, BLK, DIM OSC S1 to S37, G1, G2 OSC S1 to S37 G1, G2 Ta = 85°C (LC7574NE) Ta = 85°C (LC7574NW) Conditions Ratings –0.3 to +6.5 –0.3 to +21.0 –0.3 to +6.5 –0.3 to VDD + 0.3 –0.3 to VFL + 0.3 –0.3 to VDD + 0.3 5 67 250 150 –40 to +85 –50 to +125 Unit V V V V V V mA mA mW mW °C °C
Input voltage
Output voltage
Output current
Allowable power dissipation Operating temperature Storage temperature
Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Supply voltage Input high level voltage Input low level voltage Guaranteed oscillator range Recommended external resistance Recommended external capacitance Low level clock pulse width High level clock pulse width Data setup time Data hold time CE wait time CE setup time CE hold time BLK switching time Input voltage range Symbol VDD VFL VIH VIL fOSC ROSC COSC tøL tøH tds tdh tcp tcs tch tc VIN VDD VFL DI, CL, CE, BLK DI, CL, CE, BLK OSC OSC OSC CL: Figure 1 CL: Figure 1 DI, CL: Figure 1 DI, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 BLK, CE: Figure 3 DIM 0.5 0.5 0.5 0.5 0.5 0.5 0.5 10 0 +5.5 Conditions min 4.5 8 0.8 VDD 0 0.4 1.6 12 50 typ 5.0 12 max 5.5 18 5.5 0.2 VDD 3.0 Unit V V V V MHz kΩ pF µs µs µs µs µs µs µs µs V
Electrical Characteristics in the Allowable Operating Ranges
Parameter Input high level current Input low level current Symbol IIH IIL VOH1 Output high level voltage VOH2 VOH3 Output low level voltage Oscillator frequency Hysteresis voltage A/D converter linearity error Current drain VOL fOSC VH Err IDD Conditions DI, CL, CE, BLK, DIM: VI = 5.5 V DI, CL, CE, BLK, DIM: VI = 0 V S1 to S37: IO = 2 mA G1, G2: IO = 25 mA G1, G2: IO = 50 mA S1 to S37, G1, G2: IO = –5 µA, Ta = 25°C ROSC = 12 kΩ, COSC = 50 pF DI, CL, CE, BLK DIM Outputs open: fOSC = 1.6 MHz 0.5 –1/2 +1/2 10 –5 VFL – 0.6 VFL – 0.6 VFL – 1.3 0.125 0.25 1.6 0.5 min typ max 5 Unit µA µA V V V V MHz V LSB mA
No. 3586-2/10
LC7574NE, 7574NW Pin Assignment
1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 1
No. 3586-3/10
LC7574NE, 7574NW Block Diagram
Pin Functions
Pin No. 4 1 46 48 Pin VFL VDD VSS OSC I/O — — — I/O Function Driver block power supply. A voltage of between 8.0 and 18.0 V must be supplied. Logic block power supply. A voltage of between 4.5 and 5.5 V must be supplied. Ground. Must be connected to the system ground. Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. Display off control input BLK = low (VSS): Display off (G1 and G2 = low) BLK = high (VDD): Display on Note that serial data can be transferred while the display is turned off. Serial data transfer inputs. These pins must be connected to the system controller. CL: synchronization clock DI: transfer data CE: chip enable Handling when unused — — — VDD
47
BLK
I
GND
44 43 42
CL DI CE I
GND
45
DIM
I
When the analog dimmer is selected, the analog voltage applied to this pin controls the duty of the G1 and G2 digit output pins. Since a 6-bit A/D converter is applied to this analog voltage and that result is input to a decoder that provides a built-in dimmer curve, the relationship between the analog voltage and the duty can be specified as a mask program. Note that 63/96 · VDD is the full-scale level for the 6-bit A/D converter. Digit outputs. The frame frequency fO is (fOSC/4096) Hz Segment outputs for displaying the display data transferred by serial data input.
GND
2, 3 41 to 5
G1, G2 S1 to S37
O O
Open Open
No. 3586-4/10
LC7574NE, 7574NW Serial Data Transfer Format 1. When CL is stopped at the low level
2. When.