CY28412

www.DataSheet4U.com PRELIMINARY CY28412 Clock Generator for Intel® Grantsdale Chipset Features Supports Intel£ P4 and Prescott CPU Selectable CPU frequencies Differential CPU clock pairs 100 MHz differential SRC clocks 96 MHz differential dot clock 48 MHz USB clocks 33 MHz PCI clock CPU x2 / x3 SRC x7 / x8 PCI x8 REF x2 DOT96 x1 USB_48 x1 Low-voltage frequency select input I2C Support with read back capabilities Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction 3.3V power supply 56-pin SSOP package Block Diagram XIN XOUT CPU_STP# PCI_STP# FS_[C:A] VTT_PWRGD# IREF Pin Configuration PCI0 PCI1 VDD_PCI VDD_CPU GND_PCI CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI2 VDD_SRC PCI3 SRCT[0:6], SRCC[0:6], PCI4 SATA[T/C] PCI5 GND_PCI VDD_PCI VDD_PCI TEST_SEL/PCIF0 PCI[0:5] ITP_EN/PCIF1 VDD_PCIF PCIF[0:1] VDD_48 USB48/FS_B GND_48 VDD_48 MHz DOT96T DOT96T DOT96C DOT96C VTT_PwrGd#/PD USB_48 SRCT0 SRCC0 SRCT1 STCC1 VDD_SRC GND_SRC SRCT2 SRCC2 SATAT SATAC VDD_REF REF[1:0] XTAL OSC PLL1 PLL Ref Freq Divider Network PD PLL2 SDATA SCLK I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_REF REF0/FS_C REF1/FS_A GND_REF X1 X2 SDATA SCLK GND_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF GND_A VDD_A CPUT2_ITP/SRCT6 CPUC2_ITP/SRCC6 VDD_SRC SRCT5 SRCC5 GND_SRC SRCT4 SRCC4 SRCT3 SRCC3 VDD_SRC 56 SSOP CY28412 ...