Document
CY7C1511AV18, CY7C1526AV18 www.DataSheet4U.com CY7C1513AV18, CY7C1515AV18
72-Mbit QDR™-II SRAM 4-Word Burst Architecture
Features
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Configurations
CY7C1511AV18 – 8M x 8 CY7C1526AV18 – 8M x 9 CY7C1513AV18 – 4M x 18 CY7C1515AV18 – 2M x 36
Separate independent read and write data ports ❐ Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR-II operates with 1.5 cycle read latency when the Delay Lock Loop (DLL) is enabled Operates as a QDR-I device with 1 cycle read latency in DLL off mode Available in x 8, x 9, x 18, and x 36 configurations Full data coherency, providing most current data Core VDD = 1.8 (± 0.1V); IO VDDQ = 1.4V to VDD Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) Offered in both Pb-free and non Pb-free packages Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement
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Functional Description
The CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1511AV18), 9-bit words (CY7C1526AV18), 18-bit words (CY7C1513AV18), or 36-bit words (CY7C1515AV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
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Selection Guide
Description Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 300 MHz 300 930 940 1020 1230 278 MHz 278 865 870 950 1140 250 MHz 250 790 795 865 1040 200 MHz 200 655 660 715 850 167 MHz 167 570 575 615 725 Unit MHz mA
Cypress Semiconductor Corporation Document Number: 001-06985 Rev. *C
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198 Champion Court
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San Jose, CA 95134-1709 • 408-943-2600 Revised September 27, 2007
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Logic Block Diagram (CY7C1511AV18)
D[7:0]
8
Write Reg
Write Reg
Write Reg
Write Reg
Read Add. Decode
Write Add. Decode
A(20:0)
21
Address Register
Address Register
21
A(20:0)
2M x 8 Array
2M x 8 Array
2M x 8 Array
2M x 8 Array
K K CLK Gen.
RPS Control Logic C C CQ
DOFF
Read Data Reg. 32
VREF WPS NWS[1:0] Control Logic
16 16
Reg. Reg.
Reg. 8 8 8 8
CQ 8 Q[7:0]
Logic Block Diagram (CY7C1526AV18)
D[8:0]
9
Write Reg
Write Reg
Write Reg
Write Reg
Read Add. Decode
Write Add. Decode
A(20:0)
21
Address Register
Address Register
21
A(20:0)
2M x 9 Array
2M x 9 Array
2M x 9 Array
2M x 9 Array
K K CLK Gen.
RPS Control Logic C C CQ
DOFF
Read Data Reg. 36
VREF WPS BWS[0] Control Logic
18 18
Reg. Reg.
Reg. 9 9 9 9
CQ 9 Q[8:0]
Document Number: 001-06985 Rev. *C
Page 2 of 31
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Logic Block Diagram (CY7C1513AV18)
D[17:0]
18
Write Reg
Write Reg
Write Reg
Write Reg
Read Add. Decode
Write Add. Decode
A(19:0)
20
Address Register
Address Register
20
A(19:0)
1M x 18 Array
1M x 18 Array
1M x 18 Array
1M x 18 Array
K K CLK Gen.
RPS Control Logic C C CQ
DOFF
Read Data Reg. 72
VREF WPS BWS[1:0] Control Logic
36 36
Reg..