MAX9210

19-2864; Rev 3; 4/04 www.DataSheet4U.com Programmable DC-Balance 21-Bit Deserializers General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels. The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. Each deserializer decodes data transmitted by one of MAX9209/MAX9211/MAX9213/ MAX9215 serializers. The MAX9210/MAX9212/MAX9214/MAX9216 have rising-edge output strobes, and when DC balance is not programmed, are compatible with non-DC-balanced 21-bit deserializers such as the DS90CR216A and DS90CR218A. The MAX9220/MAX9222 have fallingedge output strobes. Two frequency versions and two DC-balance default conditions are available for maximum replacement flexibility and compatibility with popular non-DC-balanced deserializers. The transition time of the single-ended outputs is increased on the low-frequency version parts (MAX9210/ MAX9212/MAX9220) for reduced EMI. The LVDS inputs meet IEC 61000-4-2 Level 4 ESD specification, ±15kV for Air Discharge and ±8kV Contact Discharge. The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 are available in TSSOP and space-saving QFN packages, and operate over the ...