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uPSD3212A, uPSD3212C uPSD3212CV
Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
FEATURES SUMMARY
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FAST 8-BIT 8032 MCU – 40MHz at 5.0V, 24MHz at 3.3V – Core, 12-clocks per instruction DUAL FLASH MEMORIES WITH MEMORY MANAGEMENT – Place either memory into 8032 program address space or data address space – READ-while-WRITE operation for InApplication Programming and EEPROM emulation – Single voltage program and erase – 100K minimum erase cycles, 15-year retention CLOCK, RESET, AND SUPPLY MANAGEMENT – SRAM is Battery Backup capable – Normal, Idle, and Power Down Modes – Power-on and Low Voltage reset supervisor – Programmable Watchdog Timer PROGRAMMABLE LOGIC, GENERAL PURPOSE – 16 macrocells – Implements state machines, glue-logic, and so forth COMMUNICATION INTERFACES – I2C Master/Slave bus controller – Two UARTs with independent baud rate – Six I/O ports with up to 46 I/O pins – 8032 Address/Data bus available on TQFP80 package – 5 PWM outputs, 8-bit resolution – USB v1.1, low-speed 1.5Mbps, 3 endpoints (uPSD3212A only)
Figure 1. Packages
TQFP52 (T) 52-lead, Thin, Quad, Flat
TQFP80 (U) 80-lead, Thin, Quad, Flat
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JTAG IN-SYSTEM PROGRAMMING – Program the entire device in as little as 10 seconds A/D CONVERTER – Four channels, 8-bit resolution, 10µs TIMERS AND INTERRUPTS – Three 8032 standard 16-bit timers – 10 Interrupt sources with two external interrupt pins Single Supply Voltage – 4.5 to 5.5V – 3.0 to 3.6V
December 2004
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uPSD3212A, uPSD3212C, uPSD3212CV
Table 1. Device Summary
Part Number uPSD3212C-40T6 uPSD3212CV-24T6 uPSD3212C-40U6 uPSD3212CV-24U6 uPSD3212A-40T6 uPSD3212A-40U6 Max 1st 2nd SRAM Clock Flash Flash GPIO (bytes) (MHz) (bytes) (bytes) 40 24 40 24 40 40 64K 64K 64K 64K 64K 64K 16K 16K 16K 16K 16K 16K 2K 2K 2K 2K 2K 2K 37 37 46 46 37 46 USB No No No No Yes Yes 8032 Bus No No Yes Yes No Yes VCC (V) 4.5-5.5 3.0-3.6 4.5-5.5 3.0-3.6 4.5-5.5 4.5-5.5 Pkg. Temp.
TQFP52 –40°C to 85°C TQFP52 –40°C to 85°C TQFP80 –40°C to 85°C TQFP80 –40°C to 85°C TQFP52 –40°C to 85°C TQFP80 –40°C to 85°C
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TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 52-PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 uPSD3200 HARDWARE DESCRIPTION . . . . . . . . . . . . . . . ..