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HMT125V7AFP4C Dataheets PDF



Part Number HMT125V7AFP4C
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 240pin DDR3 SDRAM VLP Registered DIMM
Datasheet HMT125V7AFP4C DatasheetHMT125V7AFP4C Datasheet (PDF)

www.DataSheet4U.com 240pin DDR3 SDRAM VLP Registered DIMM DDR3 SDRAM VLP Registered DIMM Based on 1Gb A version HMT112V7AFP8C HMT125V7AFP8C HMT125V7AFP4C HMT351V7AMP4C ** Contents may be changed at any time without any notice. Rev. 0.2 / December 2008 1 www.DataSheet4U.com Revision History Revision No. 0.1 0.2 History Initial Release Added IDD, corrected typos Draft Date 2008-8 2008-12 Remark Rev. 0.2 / December 2008 2 www.DataSheet4U.com Table of Contents 1. Description 1.1 Device Fe.

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www.DataSheet4U.com 240pin DDR3 SDRAM VLP Registered DIMM DDR3 SDRAM VLP Registered DIMM Based on 1Gb A version HMT112V7AFP8C HMT125V7AFP8C HMT125V7AFP4C HMT351V7AMP4C ** Contents may be changed at any time without any notice. Rev. 0.2 / December 2008 1 www.DataSheet4U.com Revision History Revision No. 0.1 0.2 History Initial Release Added IDD, corrected typos Draft Date 2008-8 2008-12 Remark Rev. 0.2 / December 2008 2 www.DataSheet4U.com Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 1GB, 128Mx72 Module(1Rank 3.2 2GB, 256Mx72 Module(2Rank 3.3 2GB, 256Mx72 Module(1Rank 3.4 4GB, 512Mx72 Module(2Rank of of of of x8) x8) x4) x4) 4. Input/Output Capacitance & AC Parametrics 5. IDD Specifications 6. DIMM Outline Diagram 6.1 1GB, 128Mx72 Module(1Rank 6.2 2GB, 256Mx72 Module(2Rank 6.3 2GB, 256Mx72 Module(1Rank 6.4 4GB, 512Mx72 Module(2Rank of of of of x8) x8) x4) x4) Rev. 0.2 / December 2008 3 www.DataSheet4U.com 1. Description This Hynix DDR3 VLP (Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features • VDD=VDDQ=1.5V • VDDSPD=3.3V to 3.6V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmable additive latency 0, CL-1, and CL-2 sup ported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • 8K refresh cycles /64ms • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • Auto Self Refresh supported • 8 bit pre-fetch • Heat Spreader installed for 4GB • SPD with Integrated TS of Class B 1.1.2 Ordering Information # of DRAMs 9 18 18 36 # of ranks 1 2 1 2 Part Name HMT112V7AFP8C-G7/H9 HMT125V7AFP8C-G7/H9 HMT125V7AFP4C-G7/H9 HMT351V7AMP4C-G7/H9 Density 1GB 2GB 2GB 4GB Organization 128Mx72 256Mx72 256Mx72 512Mx72 Materials Lead fr.


HMT125V7AFP8C HMT125V7AFP4C HMT351V7AMP4C


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