Quad LVDS Receivers
a u s t ri a m i c r o s y s t e m s
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A S 11 5 0 , A S 11 5 1 Q u a d LV D S R e c e i v e r s
D a ...
Description
a u s t ri a m i c r o s y s t e m s
www.DataSheet4U.com
A S 11 5 0 , A S 11 5 1 Q u a d LV D S R e c e i v e r s
D a ta S he e t
1 General Description
The AS1150 and AS1151 are quad flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs and convert them to LVCMOS outputs. The receivers are perfect for lowpower low-noise applications requiring high signaling rates and reduced EMI emissions. The devices are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled impedance media of approximately 100Ω. Supported transmission media are PCB traces, backplanes, and cables. The AS1150 uses high impedance inputs and requires an external termination resistor when used in a point-topoint connection. The AS1151 features integrated parallel termination resistors (nominally 107Ω), which eliminate the requirement for discrete termination resistors, and reduce stub lengths. The integrated failsafe feature sets the output high if the inputs are open, undriven and terminated, or undriven and shorted. Enable inputs (EN and ENn – internally pulled down to GND) control the high-impedance output and are common to all four receivers. All inputs conform to the ANSI TIA/EIA- 644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The devices are available in a 16-pin TSSOP package. Figure 1. Block Diagrams
VCC
2 Key Features
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