CY7C1371DV25 www.DataSheet4U.com CY7C1373DV25
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock Pin compatible and functionally equiva...
