AD9269

Data Sheet 16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9269 FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply Integrated quadrature error correction (QEC) SNR 77.6 dBFS at 9.7 MHz input 71 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low power 44 mW per channel at 20 MSPS 100 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = −0.5/+1.1 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer (DCS) Integer 1-to-6 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock output (DCO) with programmable clock and data alignment APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA ...