Dual IF Receiver AD6659
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-bit, 80 MSPS output data rate per channel
AVDD AGND
SDIO SCLK CSB
1.8 V analog supply operation (AVDD)
SPI
CMOS OUTPUT BUFFER
1.8 V to 3.3 V output supply (DRVDD) Integrated noise shaping requantizer (NSR)
PROGRAMMING DATA
ORA
Integrated quadrature error correction (QEC) Performance wit...
