MT54W4MH8B

ADVANCE‡ www.DataSheet4U.com 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM 36Mb QDR™II SRAM 2-WORD BURST FEATURES DLL circuitry for accurate output data placement MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B Figure 1 165-Ball FBGA Separate independent read and write data ports with concurrent transactions 100 percent bus utilization DDR READ and WRITE operation Fast clock to valid data times Full data coherency, providing most current data Two-tick burst counter for low DDR transaction size Double data rate operation on read and write ports Two input clocks (K and K#) for precise DDR timing at clock rising edges only Two output clocks (C and C#) for precise flight time and clock skew matching—clock and data delivered together to receiving device Single address bus Simple control logic for easy depth expansion Internally self-timed, registered writes +1.8V core and HSTL I/O Clock-stop capability 15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package User-programmable impedance output JTAG boundary scan VALID PART NUMBERS PART NUMBER MT54W4MH8BF-xx MT54W4MH9BF-xx MT54W2MH18BF-xx MT54W1MH36BF-xx DESCRIPTION 4 Meg x 8, QDRIIb2 FBGA 4 Meg x 9, QDRIIb2 FBGA 2 Meg x 18, QDRIIb2 FBGA 1 Meg x 36, QDRIIb2 FBGA OPTIONS Clock Cycle Timing 4ns (250 MHz) 5ns (200 MHz) 6ns (167 MHz) 7.5ns (133 MHz) Configurations 4 Meg x 8 4 Meg x 9 2 Meg x 18 1 Meg x 36 Package 165-ball, 15mm x 17mm FBGA NOTE: MARKING1 -4 -5 -6 -7.5 MT5...