CY7C1411BV18

CY7C1411BV18, CY7C1426BV18 www.DataSheet4U.com CY7C1413BV18, CY7C1415BV18 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Configurations CY7C1411BV18 – 4M x 8 CY7C1426BV18 – 4M x 9 CY7C1413BV18 – 2M x 18 CY7C1415BV18 – 1M x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Single multiplexed address input bus latches address inputs for both read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR-II operates with 1.5 cycle read latency when DLL is enabled Operates as a QDR-I device with 1 cycle read latency in DLL off mode Available in x 8, x 9, x 18, and x 36 configurations Full data coherency, providing most current data Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) Offered in both Pb-free and non Pb-free packages Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement ■ ■ ■ ■ Functional Description The CY7C1411BV18, CY7C1426BV18, CY7C1...