CY7C1415AV18

CY7C1411AV18, CY7C1426AV18 www.DataSheet4U.com CY7C1413AV18, CY7C1415AV18 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Functional Description The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support the read operations and the write port has dedicated data inputs to support the write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1411AV18), 9-bit words (CY7C1426AV18), 18-bit words (CY7C1413AV18), or 36-bit words (CY7C1415AV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with port selects, which ena...