Document
NB7L585R 2.5V/3.3V, 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer / Translator
Multi−Level Inputs w/ Internal Termination
Description
http://onsemi.com MARKING DIAGRAM
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The NB7L585R is a differential 1:6 RSECL Clock/Data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels. The NB7L585R produces six identical output copies of Clock or Data operating up to 7 GHz or 10 Gb/s, respectively. As such, NB7L585R is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The NB7L585R is powered with either 2.5 V or 3.3 V supply and is offered in a low profile 5mm x 5mm 32−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7L585R is a member of the GigaComm™ family of high performance clock products.
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32
QFN32 MN SUFFIX CASE 488AM
NB7L 585R AWLYYWWG G
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location)
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SEL Q0 VREFAC0 IN0 VT0 IN0 50 W 50 W
• Maximum Input Data Rate > 10 Gb/s Typical • Data Dependent Jitter < 10 ps • Maximum Input Clock Frequency > 7 GHz Typical • Random Clock Jitter < 0.8 ps RMS www.DataSheet4U.com • Low Skew 1:6 RSECL Outputs, 20 ps max • 2:1 Multi−Level Mux Inputs • 160 ps Typical Propagation Delay • 40 ps Typical Rise and Fall Times • Differential RSECL Outputs, 400 mV peak−to−peak, typical • Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V • Internal 50 W Input Termination Resistors • VREFAC Reference Output • QFN−32 Package, 5mm x 5mm • −40ºC to +85ºC Ambient Operating Temperature • These Devices are Pb−Free and are RoHS Compliant
Features
Q0 Q1 0 Q1 Q2
IN1 VT1 IN1
Q2 Q3 50 W 50 W 1 Q3 Q4
VREFAC1 VCC GND Q4 Q5
Q5
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
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October, 2009 − Rev. 0
Publication Order Number: NB7L585R/D
NB7L585R
GND VCC VCC SEL Q0 Q0 Q1 Q1 Exposed Pad (EP)
Table 1. INPUT SELECT FUNCTION TABLE
SEL* 0 CLK Input Selected IN0 IN1
32 IN0 VT0 VREFAC0 IN0 IN1 VT1 VREFAC1 IN1 1 2 3 4 5 6 7 8 9 GND
31
30
29
28
27
26
25 24 23 22 21 20 19 18 17 GND VCC Q2 Q2 Q3 Q3 VCC GND
1 *Defaults HIGH when left open.
NB7L585R
10 NC
11 VCC
12 Q5
13 Q5
14 Q4
15 Q4
16 VCC
Figure 2. Pinout: QFN−32 (Top View) Table 2. PIN DESCRIPTION
Pin Number 1,4 5,8 2,6 31 10 11, 16, 18 23, 25, 30 29, 28 27, 26 22, 21 20, 19 15, 14 www.DataSheet4U.com 13, 12 9, 17, 24, 32 3 7 − Pin Name IN0, IN0 IN1, IN1 VT0, VT1 SEL NC VCC Q0, Q0 Q1, Q1 Q2,Q2 Q3, Q3 Q4, Q4 Q5, Q5 GND VREFAC0 VREFAC1 EP − − LVTTL/LVCMOS Input − − RSECL Output I/O LVPECL, CML, LVDS Input Pin Description Non−inverted, Inverted, Differential Data Inputs internally bi.