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NB7VPQ16M Dataheets PDF



Part Number NB7VPQ16M
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver
Datasheet NB7VPQ16M DatasheetNB7VPQ16M Datasheet (PDF)

NB7VPQ16M 1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver with Selectable Equalizer Receiver Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 16 1 The NB7VPQ16M is a high performance single channel programmable Pre−Emphasis CML Driver with a selectable Equalizer Receiver that operates up to 14 Gbps typical with a 1.8 V or 2.5 V power supply. When placed in series with a Data/Clock path, the NB7VPQ16M inputs will compensate the degra.

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NB7VPQ16M 1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver with Selectable Equalizer Receiver Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 16 1 The NB7VPQ16M is a high performance single channel programmable Pre−Emphasis CML Driver with a selectable Equalizer Receiver that operates up to 14 Gbps typical with a 1.8 V or 2.5 V power supply. When placed in series with a Data/Clock path, the NB7VPQ16M inputs will compensate the degraded signal transmitted across a FR4 PCB backplane or cable interconnect. Therefore, the serial data rate is increased by reducing Inter−Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The Pre−Emphasis buffer is controlled using a serial bus via the Serial Data In (SDIN) and Serial Clock In (SCLKIN) control inputs and contains circuitry which provides sixteen programmable Pre−Emphasis settings to select the optimal output compensation level. These selectable output levels will handle various backplane lengths and cable lines. The first four SDIN bits (D3:D0) will digitally select 0 dB through 12 dB typical of de−emphasis (see Table 1). For cascaded applications, the shifted SDIN and SCLKIN signals are presented at the SDOUT and SCLKOUT pins. The 5th−bit (LSB) of the serial data bits allows for enabling the equalization function of the receiver. The differential Data / Clock inputs incorporate a pair of internal www.DataSheet4U.com 50 W termination resistors, in a 100 W center−tapped configuration, via the VT pin and will accept LVPECL, CML or LVDS logic levels. This feature provides transmission line termination on−chip, at the receiver end, eliminating external components. The NB7VPQ16M is a member of the GigaComm™ Family of high performance Data/Clock products with Pre−Emphasis/Equalization (PEEQ). Features 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7V PQ16M ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. SDOUT SDI SCLKOUT DAC Q IN EQ PE Q IN VT SDIN SCLKIN SLOAD Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. • • • • • • Maximum Input Data Rate > 12.5 Gbps Maximum Input Clock Frequency > 8 GHz Drives Up To 18−inches of FR4 (16) Programmable Output De−emphasis Levels; 0 dB through 12 dB 200 ps Typical Propagation Delay Differential CML Outputs, 400 mV Peak−to−Peak, Typical (PE = 0 dB) • • • • • Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V Internal Output Termination Resistors, 50 W QFN−16 Package, 3 mm x 3 mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 0 1 Publication Order Number: NB7VPQ16M/D NB7VPQ16M (15) SDIN (14) SCLKIN VCCD VCC GND Multi−Level Inputs LVPECL, LVDS, CML (2) IN (1) VT (3) IN 5−Bit Shift Register EQEN D0 D1 D2 D3 SDOUT (6) SCLKOUT (7) (13) SLOAD D/A Latch EQEN (EQualizer ENable) 4−Bit DAC Q (11) Q (10) CML Output 50W 50W EQ 0 2:1 MUX 1 Pre−Emphasis Control Figure 2. Detailed Block Diagram of NB7VPQ16M Q Low Q High Bit n −1 Q High Q Low Bit n Q High Q Low Bit n+1 Q Low Q High Bit n+2 PE = 0dB PE = −12dB Q 20% 80% 0V VOD0dB VODPE www.DataSheet4U.com Q tPE X130ps PE = 20log(VODPE/VOD0dB) VOD0dB − Differential Output Voltage without Pre−Emphasis VODPE − Differential Output Voltage with Pre−Emphasis Figure 3. Illustration of Output Waveform Definition http://onsemi.com 2 NB7VPQ16M Table 1. TYPICAL PRE−EMPHASIS CONTROL TABLE, EQ = 0, 255C, VCC = 1.8 V 4−bit PE MSB Decimal 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PE Output Compensation in dB Approximate @ 1 GHz 0 dB (Default) −1.0 dB −1.5 dB −2.0 dB −2.5 dB −3.0 dB −3.5 dB −4.0 dB −4.5 dB −5.0 dB −6.0 dB −7.0 dB −8.0 dB −9.0 dB −10.0 dB −12.0 dB VODPE Typ (mV) 435 390 365 345 325 310 290 275 260 245 220 195 175 155 135 110 Table 2. EQUALIZER ENABLE FUNCTION EQEN 0 1 Function IN/IN Inputs By−pass the Equalizer section Inputs flow through the Equalizer www.DataSheet4U.com http://onsemi.com 3 NB7VPQ16M SCLKIN SLOAD SDIN VCC Exposed Pad (EP) 16 VT IN IN GND 1 2 15 14 13 12 VCC 11 Q 10 Q 9 VCC NB7VPQ16M 3 4 5 VCCD 6 SDOUT 7 SCLKOUT 8 GND Figure 4. Pin Configuration (Top View) Table 3. PIN DESCRIPTION Pin 1 2 3 4 5 6 Name VT IN IN GND VCCD SDOUT LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − − LVCMOS Output LVCMOS Output − − CML CML − LVCMOS Input I/O Description Internal 50−W Termination Pin for IN and IN Non−inverted Differential Clock/Data Input. (Note 1) Inverted Differential Clock/Data Input. (Note 1) Negative Supply Voltage; (Note 2) Positive Supply Voltage for Seri.


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