Document
2.5 V/3.3 V 1:8 CML Fanout
Multi−Level Inputs w/ Internal Termination
NB7L1008M
Description The NB7L1008M is a high performance differential 1:8 Clock/Data
fanout buffer. The NB7L1008M produces eight identical output copies of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7L1008M to accept various logic standards, such as LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. The 1:8 fanout design was optimized for low output skew applications. The NB7L1008M is a member of the GigaComm™ family of high performance clock products.
Features
• Input Data Rate > 12 Gb/s Typical • Data Dependent Jitter < 20 ps • Maximum Input Clock Frequency > 8 GHz Typical • Random Clock Jitter < 0.8 ps RMS • Low Skew 1:8 CML Outputs, < 25 ps max • Multi−Level Inputs, accepts LVPECL, CML, LVDS • 160 ps Typical Propagation Delay • 45 ps Typical Rise and Fall Times • Differential CML Outputs, 400 mV Peak−to−Peak, Typical • Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V • Internal Input Termination Resistors, 50 W • VREFAC Reference Output • QFN−32 Package, 5 mm x 5 mm • −40°C to +85°C Ambient Operating Temperature • These are Pb−Free Devices
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1 32
QFN32 MN SUFFIX CASE 488AM
MARKING DIAGRAM*
32
1
NB7L 1008M AWLYYWWG
G
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
SIMPLIFIED LOGIC DIAGRAM
Q0 Q0
Q1 Q1
Q2 Q2
IN
Q3
Q3
50W
VT
50W
IN
Q4
Q4 VREFAC
Q5 Q5
Q6 Q6
Q7 Q7
© Semiconductor Components Industries, LLC, 2013
May, 2021 − Rev. 2
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of this data sheet.
1
Publication Order Number:
NB7L1008M/D
NB7L1008M
Exposed Pad (EP)
VCC Q0 Q0 Q1 Q1 Q2 Q2 VCC
32 31 30 29 28 27 26 25
VCC 1
24 GND
GND 2
23 VCC
IN 3
22 Q3
VT 4 VREFAC 5
NB7L1008M
21 Q3 20 Q4
IN 6
19 Q4
GND 7
18 VCC
VCC 8
17 GND
9 10 11 12 13 14 15 16
VCC Q7 Q7 Q6 Q6 Q5 Q5
VCC
Figure 1. 32−Lead QFN Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
3, 6
IN, IN
LVPECL, CML, Non−inverted / Inverted Differential Clock/Data Input. Note 1
LVDS Input
4
VT
Internal 50 W Termination Pin for IN and IN
2, 7 17,24
GND
Negative Supply Voltage. (Note 2)
1, 8, 9, 16, 18,
VCC
23, 25, 32
Positive Supply Voltage. (Note 2)
31, 30, 29, 28, 27, 26, 22, 21, 20, 19, 15, 14, 13, 12, 11, 10
Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6, Q7, Q7
CML
Non−inverted / Inverted Differential Output. (Note 1)
5
VREFAC
Output Voltage Reference for Capacitor−Coupled Inputs, only
−
EP
−
The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to GND and is
recommended to be electrically connected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN/IN, then the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50 W source termination resistors.
2. All VCC and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.
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NB7L1008M
Table 2. ATTRIBUTES
Characteristics
ESD Protection Human Body Model Machine Model
Moisture Sensitivity (Note 3) Indefinite Time of the Drypack QFN−32
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, refer to Application Note AND8003/D.
Value
> 2 kV > 200 V
Level 1
UL 94 V−0 @ 0.125 in 263
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC VIN VINPP IIN Iout
Positive Power Supply Input Voltage Differential Input Voltage |IN − IN| Input Current Through RT (50 W Resistor) Output Current
GND = 0 V GND = 0 V
Continuous Surge
4.0
V
−0.5 to VCC
V
1.89
V
±40
mA
34
mA
40
IVFREFAC TA Tstg qJA
VREFAC Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4) TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias
0 lfpm 500 lfpm
QFN−32 QFN−32
±1.5
−40 to +85
−65 to +150
31 27
mA
°C
°C
°C/W °C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board QFN−32
12
°C/W
Tsol
Wave Solder
Pb−Free
265
°C
Stresses exceeding those lis.