SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at
70 MHz @ 150 MSPS
SFDR = 80 dBc to 70 MHz @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
Integer 1-to-8 input clock divider
Integrated dual-channel ADC
Sample rates up to 150 MSPS
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC)
32-bit complex, numerically controlled oscillator (NCO)
Decimating half-band filter and FIR filter
Supports real and complex output modes
Fast attack/threshold detect bits
Composite signal monitor
Energy-saving power-down modes
IF Diversity Receiver
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
1. Integrated dual, 14-bit, 150 MSPS ADC.
2. Integrated wideband decimation filter and 32-bit
3. Fast overrange detect and signal monitor with serial output.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Flexible output modes, including independent CMOS,
interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
6. SYNC input allows synchronization of multiple devices.
7. 3-bit SPI port for register programming and register readback.
FUNCTIONAL BLOCK DIAGRAM
HB FILTER +
HB FILTER +
FD BITS/THRESHOLD SIGNAL MONITOR
SMI SMI SMI
SDFS SCLK/ SDO/
SDIO/ SCLK/ CSB
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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