Document
FEATURES
11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer (NSR) Performance with NSR enabled
SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS Performance with NSR disabled SNR: 66.5 dBFS to 70 MHz @ 185 MSPS SFDR: 83 dBc to 70 MHz @ 185 MSPS Low power: 0.62 W @ 185 MSPS 1.8 V analog supply operation 1.8 V LVDS (ANSI-644 levels) output 1-to-8 integer clock divider Internal ADC voltage reference 1.75 V p-p analog input range (programmable to 2.0 V p-p) Differential analog inputs with 800 MHz bandwidth 95 dB channel isolation/crosstalk Serial port control User-configurable built-in self-test (BIST) capability Energy-saving power-down modes
APPLICATIONS
Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios
Dual IF Receiver AD6642
DATA MULTIPLEXER AND LVDS DRIVERS
08563-001
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DRVDD DRGND
VIN+A VIN–A VCMA VIN+B VIN–B VCMB
AD6642
14
11
PIPELINE
NOISE SHAPING
ADC
REQUANTIZER
14 PIPELINE
NOISE SHAPING 11
ADC
REQUANTIZER
REFERENCE SERIAL PORT
CLOCK DIVIDER
DC0±AB D0±AB
D10±AB
MODE SYNC PDWN
SCLK SDIO CSB
Figure 1.
CLK+ CLK–
PRODUCT HIGHLIGHTS
1. Two ADCs are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.
2. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.
3. LVDS digital output interface configured for low cost FPGA families.
4. 120 mW per ADC core power consumption. 5. Operation from a single 1.8 V supply. 6. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. 7. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.
Rev. A
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AD6642
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4
DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Specifications .................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 15 Theory of Operation ...................................................................... 16 ADC Architecture ...................................................................... 16 Analog Input Considerations.................................................... 16 Clock Input Considerations ...................................................... 18
REVISION HISTORY
7/10—Rev. 0 to Rev. A Changes to ADC Architecture Section........................................ 16 Changes to Figure 34 and Figure 35......................