CG6257AM

PRELIMINARY CG6257AM 4Mb (256K x 16) Pseudo Static RAM Features Wide voltage range: 2.70V–3.30V Access Time: 70ns Ultra-low active power — Typical active current: 2.0mA @ f = 1 MHz — Typical active current: 13mA @ f = fmax Ultra low standby power Automatic power-down when deselected CMOS for optimum speed/power Offered in a 48 Ball BGA Package when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH ), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The addresses must not be toggled once the read is started on the device. Writing to the device is accomplished by taking Chip Enables (CE LOW ) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enables (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will ap...