CY7C1379C

CY7C1379C 9-Mbit (256K x 32) Flow-through SRAM with NoBL™ Architecture Features Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock Pin compatible and functionally equivalent to ZBT™ devices Internally self-timed output buffer control to eliminate the need to use OE Registered inputs for flow-through operation Byte Write capability 256K x 32 common I/O architecture Single 3.3V power supply (VDD) Fast clock-to-output times — 6.5 ns (for 133-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous Output Enable Available in JEDEC-standard lead-free 100-Pin TQFP, lead-free and non lead-free 165-Ball FBGA package Burst Capability—linear or interleaved burst order Low standby power Functional Description[1] The CY7C1379C is a 3.3V, 256K x 32 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1379C is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) sign...