CY7C1378C

CY7C1378C 9-Mbit (256K x 32) Pipelined SRAM with NoBL™ Architecture Features Pin-compatible and functionally equivalent to ZBT® devices Internally self-timed output buffer control to eliminate the need to use OE Byte Write capability 256K x 32 common I/O architecture Single 3.3V power supply (VDD) Fast clock-to-output times — 2.8 ns (for 250-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous Output Enable (OE) Available in JEDEC-standard lead-free 100-Pin TQFP package Burst Capability—linear or interleaved burst order “ZZ” Sleep mode option Functional Description[1] The CY7C1378C is a 3.3V, 256K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1378C is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from...