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R2J20604NP Dataheets PDF



Part Number R2J20604NP
Manufacturers Renesas Technology
Logo Renesas Technology
Description Integrated Driver MOSFET
Datasheet R2J20604NP DatasheetR2J20604NP Datasheet (PDF)

R2J20604NP Integrated Driver – MOS FET (DrMOS) REJ03G1605-0400 Rev.4.00 Mar 12, 2010 Description The R2J20604NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this.

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R2J20604NP Integrated Driver – MOS FET (DrMOS) REJ03G1605-0400 Rev.4.00 Mar 12, 2010 Description The R2J20604NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose. Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the package standard “Integrated Driver – MOS FET (DrMOS)” proposed by Intel Corporation. Features  Built-in power MOS FET suitable for applications with 12 V input and low output voltage  Built-in driver circuit which matches the power MOS FET  Built-in tri-state input function which can support a number of PWM controllers  Capable of 3.3 V PWM signal  VIN operating-voltage range: 16 V max  High-frequency operation (above 1 MHz) possible  Large average output current (Max. 40 A)  Achieve low power dissipation (About 4.4 W at 1 MHz, 25 A)  Controllable driver: Remote on/off  Built-in Schottky diode for bootstrapping  Low-side drive voltage can be independently set  Small package: QFN56 (8 mm  8 mm  0.95 mm)  Terminal Pb-free/Halogen-free Outline VCIN BOOT GH VIN 1 14 Reg5V 56 15 Driver Tab High-side MOS Tab DISBL# PWM MOS FET Driver VSWH Low-side MOS Tab 43 28 CGND VLDRV GL PGND 42 29 (Bottom view) QFN56 package 8 mm × 8 mm REJ03G1605-0400 Rev.4.00 Mar 12, 2010 Page 1 of 14 R2J20604NP Block Diagram VCIN Reg5V BOOT GH Driver chip DISBL# 2 µA CGND UVL 5 V Gen. SBD Level shifter VIN High-side MOS FET PWM VCIN Input logic (TTL level) (3 state in) Overlap protection CGND VLDRV GL Notes: 1. Truth table for the DISBL# pin. DISBL# Input Driver Chip Status “L” Shutdown (GL, GH = “L”) “Open” Shutdown (GL, GH = “L”) “H” Enable (GL, GH = “Active”) 2. Output signal from the UVL block "H" UVL Output Logic Level For shutdown "L" For activation VL VH VCIN VSWH Low-side MOS FET PGND REJ03G1605-0400 Rev.4.00 Mar 12, 2010 Page 2 of 14 R2J20604NP Pin Arrangement VIN VIN VIN VIN VIN VIN VIN GH CGND BOOT VCIN VLDRV NC CGND 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VIN 15 VIN 16 VIN 17 VIN 18 VIN 19 VIN 20 VSWH 21 PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND 28 VIN CGND VSWH 56 PWM 55 DISBL# 54 Reg5V 53 NC 52 GL 51 CGND 50 VSWH 49 VSWH 48 VSWH 47 VSWH 46 VSWH 45 VSWH 44 VSWH 43 VSWH 29 30 31 32 33 34 35 36 37 38 39 40 41 42 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND VSWH VSWH VSWH (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name CGND NC VLDRV Pin No. 1, 6, 51, Tab 2, 53 3 VCIN BOOT GH VIN VSWH PGND GL Reg5V DISBL# PWM 4 5 7 8 to 20, Tab 21, 40 to 50, Tab 22 to 39 52 54 55 56 Description Control signal ground No connect Low side gate supply voltage Control input voltage (+12 V input) Bootstrap voltage pin High side gate signal Input voltage Phase output/Switch output Power ground Low side gate signal +5 V logic power supply output Signal disable PWM drive logic input Remarks Should be connected to PGND externally For 5 V to 12 V gate drive voltage for Low side gate driver Driver Vcc input To be supplied +5 V through internal SBD Pin for Monitor Pin for Monitor Disabled when DISBL# is “L” REJ03G1605-0400 Rev.4.00 Mar 12, 2010 Page 3 of 14 R2J20604NP Absolute Maximum Ratings Item Symbol Rating Units Power dissipation Pt(25) 25 W Pt(110) 8 W Average output current Iout 40 A Input voltage VIN (DC) –0.3 to +16 V VIN (AC) 20 Supply voltage VCIN (DC) –0.3 to +16 V VCIN (AC) 20 Low side driver voltage VLDRV (DC) –0.3 to +16 V VLDRV (AC) 20 Switch node voltage VSWH (DC) 16 V VSWH (AC) 20 BOOT voltage VBOOT (DC) 22 V VBOOT (AC) 25 DISBL# voltage Vdisble –0.3 to VCIN V PWM voltage Vpwm –0.3 to +5.5 V –0.3 to +0.3 V Reg5V current Ireg5V –10 to +0.1 mA Operating junction temperature Tj-opr –40 to +150 °C Storage temperature Tstg –55 to +150 °C Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. 2. Rated voltages are relative to voltages on the CGND and PGND pins. 3. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. 4. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode). 5. This rating is when UVL (Under Voltage Lock out) is effective (lock out mode). 6. The specification values indicated “AC” are limited within 100 ns. (Ta = 25°C) Note 1 1 2 2, 6 2 2, 6 2 2, 6 2 2, 6 2 2, 6 2 2, 4 2, 5 3 Average Output Current (A) 45 40 35 30 25 20 15 10 5 0 0 Safe Operating Area Condition VOUT = 1.3 V VIN = 12 V VLDRV = 5 V VCIN = .


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