IS43R16160A

IS43R16160A 16Meg x 16 256-MBIT DDR SDRAM FEATURES ISSI DEVICE OVERVIEW ® PRELIMINARY INFORMATION NOVEMBER 2005 Clock Frequency: 200, 166 MHz Power supply (VDD and VDDQ) DDR 333: 2.5V + 0.2V DDR 400: 2.6V + 0.1V SSTL 2 interface Four internal banks to hide row Pre-charge and Active operations Commands and addresses register on positive clock edges (CK) Bi-directional Data Strobe signal for data capture Differential clock inputs (CK and CK) for two data accesses per clock cycle Data Mask feature for Writes supported DLL aligns data I/O and Data Strobe transitions with clock inputs Half-strength and Full-strength drive strength options Programmable burst length for Read and Write operations Programmable CAS Latency (2, 2.5, or 3 www.DataSheet4U.com clocks) Programmable burst sequence: sequential or interleaved Burst concatenation and truncation supported for maximum data throughput Auto Pre-charge option for each Read or Write burst 8192 refresh cycles every 64ms ISSI’s 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The d...