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NBXDPA018 Dataheets PDF



Part Number NBXDPA018
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description LVDS Clock Oscillator
Datasheet NBXDPA018 DatasheetNBXDPA018 Datasheet (PDF)

NBXDPA018 2.5 V / 3.3 V, 155.52 MHz / 311.04 MHz LVDS Clock Oscillator The NBXDPA018 dual frequency crystal oscillator (XO) is designed to meet today’s requirements for 2.5 V and 3.3 V LVDS clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 155.52 MHz or 311.04 MHz, ultra low jitter and phase noise LVDS differential output. This device is a member of ON Semiconductor’s PureEdget clock family that provides accurat.

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NBXDPA018 2.5 V / 3.3 V, 155.52 MHz / 311.04 MHz LVDS Clock Oscillator The NBXDPA018 dual frequency crystal oscillator (XO) is designed to meet today’s requirements for 2.5 V and 3.3 V LVDS clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 155.52 MHz or 311.04 MHz, ultra low jitter and phase noise LVDS differential output. This device is a member of ON Semiconductor’s PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1000. Features http://onsemi.com MARKING DIAGRAM NBXDPA018 155.52/311.04 AWLYYWW 6 PIN CLCC LN SUFFIX CASE 848AB NBXDPA018 155.52/311.04 A WL YY WW G or G • • • • • • • • • LVDS Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz) Selectable Output Frequency − 155.52 MHz (default) / 311.04 MHz Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range: 2.5 V ±5% Operating Range: 3.3 V ±10% Total Frequency Stability − $50 ppm This is a Pb−Free Device = NBXDPA018 (±50 PPM) = Output Frequency (MHz) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device NBXDPA018LN1TAG NBXDPA018LNHTAG Package CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) Shipping† 1000/ Tape & Reel 100/ Tape & Reel • SONET Line Card • Networking www.DataSheet4U.com • Optical Systems VDD 6 CLK CLK 5 4 Applications †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Crystal PLL Clock Multiplier 1 OE 2 FSEL 3 GND Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 0 1 Publication Order Number: NBXDPA018/D NBXDPA018 OE FSEL GND 1 2 3 6 5 4 VDD CLK CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin No. 1 2 3 4 5 6 Symbol OE I/O Description LVTTL/LVCMOS Control Input LVTTL/LVCMOS Control Input Power Supply LVDS Output LVDS Output Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. FSEL GND CLK CLK VDD Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output Frequency Select pin description Table 3. Ground 0 V Non−Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. Positive power supply voltage. Voltage should not exceed 2.5 V ±5% or 3.3 V ±10%. Power Supply Table 2. OUTPUT ENABLE TRI−STATE FUNCTION OE Pin Open HIGH Level LOW Level Output Pins Active Active High Z Table 3. OUTPUT FREQUENCY SELECT FSEL Pin Open (pin will float high) HIGH Level LOW Level Output Frequency (MHz) 155.52 155.52 311.04 Table 4. ATTRIBUTES Characteristic www.DataSheet4U.com Input Default State Resistor ESD Protection Human Body Model Machine Model Value 170 kW 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VDD Iout TA Tstg Tsol Parameter Positive Power Supply LVDS Output Current Operating Temperature Range Storage Temperature Range Wave Solder See Figure 6 Condition 1 GND = 0 V Continuous Surge Condition 2 Rating 4.6 25 50 −40 to +85 −55 to +120 260 Units V mA °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 NBXDPA018 Table 6. DC CHARACTERISTICS (VDD = 2.5 V ± 5% or VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 2) Symbol IDD VIH VIL IIH IIL DVOD Characteristic Power Supply Current OE and FSEL Input HIGH Voltage OE and FSEL Input LOW Voltage Input HIGH Current Input LOW Current OE FSEL OE FSEL 2000 GND − 300 −100 −100 −100 −100 0 1 Conditions Min. Typ. 85 Max. 105 VDD 800 +100 +100 +100 +100 25 Units mA mV mV mA mA mV Change in Magnitude of VOD for Complementary Output States (Note 3) Offset Voltage Change in Magnitude of VOS for Complementary Output States (Note 3) Output HIGH Voltage Output LOW Voltage Differential Output Voltage VDD = 2.5 V VDD = 3.3 V VDD = 2.5 V VDD = 3.3 V VOS DVOS 1125 0 1 1375 25 mV mV .


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