BLD6G21L-50

BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Rev. 01 — 28 October 2009 Objective data sheet 1. Product profile 1.1 General description The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution using NXP’s state of the art GEN6 LDMOS technology. This device is perfectly suited for TD-SCDMA base station applications at frequencies from 2010 MHz to 2025 MHz. The main and peak device, input splitter and output combiner are integrated in a single package. This package consists of one gate and drain lead and two extra leads of which one is used for biasing the peak amplifier and the other is not connected. It only requires the proper input/output match and bias setting as with a normal class-AB transistor. Table 1. Typical performance RF performance at Th = 25 °C. Mode of operation TD-SCDMA [1] [2] [1][2] f (MHz) 2010 to 2025 VDS (V) 28 PL(AV) (W) 8 Gp (dB) 13.5 ηD (%) 42 ACPR (dBc) −23 PL(3dB) (W) 50 Test signal: 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. IDq = 170 mA (main); VGS(amp)peak = 0 V. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. www.DataSheet4U.com 1.2 Features I Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz: N Average output power = 8 W N Power gain = 13.5 dB N Efficiency = 42 % I Fully optimized integrated Doherty concept: N integrated asymmetrical power splitter ...