DatasheetsPDF.com

UPD161641 Dataheets PDF



Part Number UPD161641
Manufacturers NEC
Logo NEC
Description 240-OUTPUT TFT-LCD GATE DRIVER
Datasheet UPD161641 DatasheetUPD161641 Datasheet (PDF)

DATA SHEET MOS INTEGRATED CIRCUIT µPD161641 240-OUTPUT TFT-LCD GATE DRIVER DESCRIPTION The µPD161641 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. FEATURES • High breakdown voltage output (VT-VB = 37 V MAX.) • 3.0 V CMOS level input • Number of output: 240 # ORDERING INFORMATION Part number Package TCP (TAB package) Chip µPD161641N-xxx µPD161641P Remark Purchasing t.

  UPD161641   UPD161641



Document
DATA SHEET MOS INTEGRATED CIRCUIT µPD161641 240-OUTPUT TFT-LCD GATE DRIVER DESCRIPTION The µPD161641 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. FEATURES • High breakdown voltage output (VT-VB = 37 V MAX.) • 3.0 V CMOS level input • Number of output: 240 # ORDERING INFORMATION Part number Package TCP (TAB package) Chip µPD161641N-xxx µPD161641P Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives. www.DataSheet4U.com The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15678EJ1V0DS00 (1st edition) Date Published July 2002 NS CP(K) Printed in Japan The mark # shows major revised points. © 2001 µPD161641 1. BLOCK DIAGRAM R,/L CLK STVSEL STVR SR1 SR2 SR87 SR88 SR89 SR90 SR239 SR240 STVL MPX OE1SEL OE1 OE2SEL OE2 VEE VSS VCC1 VT PVSS PVCC1 VB Level Shifter O1 O2 O87 O88 O89 O90 O239 O240 www.DataSheet4U.com Remark /xxx indicates active low signal. 2 Data Sheet S15678EJ1V0DS µPD161641 2. PIN CONFIGURATION (Pad Layout) Chip size: 9.4 x 3.5 mm 2 2 Bump size: INPUT (include input side dummy and short-side dummy): 49 x 85 µm OUTPUT (include output side dummy): 35 x 94 µm No.123 Face Up No.122 2 No.380 Y X (0,0) No.381 No.119 No.384 No.118 No.1 Alignment Mark 30 µm 30 µm 30 µm 30 µm 30 µm 30 µm www.DataSheet4U.com Data Sheet S15678EJ1V0DS 3 µPD161641 Table 2 Gate Inputs 75 µm pich Pad Name X [mm] Alignment Mark 1. Pad Layout (1/4) Gate Inputs 75 µm pich Pad Name X [mm] DUMMY -0.4875 DUMMY -0.5625 DUMMY -0.6375 DUMMY -0.7125 VEE -0.7875 VEE -0.8625 VEE -0.9375 VEE -1.0125 VEE -1.0875 DUMMY -1.1625 DUMMY -1.2375 VB -1.3125 VB -1.3875 VB -1.4625 VB -1.5375 VB -1.6125 DUMMY -1.6875 DUMMY -1.7625 DUMMY -1.8375 STVR -1.9125 STVR -1.9875 STVR -2.0625 STVR -2.1375 STVR -2.2125 DUMMY -2.2875 STVL -2.3625 STVL -2.4375 STVL -2.5125 STVL -2.5875 STVL -2.6625 DUMMY -2.7375 CLK -2.8125 CLK -2.8875 CLK -2.9625 CLK -3.0375 CLK -3.1125 DUMMY -3.1875 OE1 -3.2625 OE1 -3.3375 OE1 -3.4125 OE1 -3.4875 OE1 -3.5625 DUMMY -3.6375 OE2 -3.7125 OE2 -3.7875 OE2 -3.8625 OE2 -3.9375 OE2 -4.0125 DUMMY -4.0875 DUMMY -4.1625 DUMMY -4.2375 DUMMY -4.3125 DUMMY -4.3875 Alignment Mark Pad No. - Y [mm] -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 4.5650 4.3875 4.3125 4.2375 4.1625 4.0875 4.0125 3.9375 3.8625 3.7875 3.7125 3.6375 3.5625 3.4875 3.4125 3.3375 3.2625 3.1875 3.1125 3.0375 2.9625 2.8875 2.8125 2.7375 2.6625 2.5875 2.5125 2.4375 2.3625 2.2875 2.2125 2.1375 2.0625 1.9875 1.9125 1.8375 1.7625 1.6875 1.6125 1.5375 1.4625 1.3875 1.3125 1.2375 1.1625 1.0875 1.0125 0.9375 0.8625 0.7875 0.7125 0.6375 0.5625 0.4875 0.4125 0.3375 0.2625 0.1875 0.1125 0.0375 -0.0375 -0.1125 -0.1875 -0.2625 -0.3375 -0.4125 1 DUMMY 2 DUMMY 3 DUMMY 4 DUMMY 5 DUMMY 6 DUMMY 7 DUMMY 8 DUMMY 9 DUMMY 10 DUMMY 11 DUMMY 12 DUMMY 13 DUMMY 14 DUMMY 15 DUMMY 16 DUMMY 17 DUMMY 18 DUMMY 19 PVCC1 20 OE1SEL 21 OE1SEL 22 OE1SEL 23 OE1SEL 24 OE1SEL 25 PVSS 26 OE2SEL 27 OE2SEL 28 OE2SEL 29 OE2SEL 30 OE2SEL 31 DUMMY 32 PVCC1 33 STVSEL 34 STVSEL 35 STVSEL 36 STVSEL 37 STVSEL 38 PVSS 39 R,/L 40 R,/L 41 R,/L 42 R,/L 43 R,/L www.DataSheet4U.com 44 PVCC1 45 DUMMY 46 VT 47 VT 48 VT 49 VT 50 VT 51 DUMMY 52 DUMMY 53 VCC1 54 VCC1 55 VCC1 56 VCC1 57 VCC1 58 DUMMY 59 DUMMY 60 DUMMY 61 VSS 62 VSS 63 VSS 64 VSS 65 VSS Pad No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 − Y [mm] -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -1.6145 -4.5650 4 Data Sheet S15678EJ1V0DS µPD161641 Table 2−1. Pad Layout (2/4) Pad No. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143.


UPD161623 UPD161641 UPD161643


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)