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DS92LV3222 Dataheets PDF



Part Number DS92LV3222
Manufacturers National Semiconductor Corporation
Logo National Semiconductor Corporation
Description (DS92LV3221 / DS92LV3222) 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer
Datasheet DS92LV3222 DatasheetDS92LV3222 Datasheet (PDF)

DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer October 21, 2009 DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer General Description The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.6 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variati.

  DS92LV3222   DS92LV3222



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DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer October 21, 2009 DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer General Description The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.6 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus. On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation. By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in ATSPEED BIST feature validates link integrity and may be used for system diagnostics. Features ■ Wide Operating Range Embedded Clock SER/DES — Up to 32-bit parallel LVCMOS data — 20 to 50 MHz parallel clock — Up to 1.6 Gbps application data paylod Simplified Clocking Architecture — No separate serial clock line — No reference clock required — Receiver locks to random data On-chip Signal Conditioning for Robust Serial Connectivity — Transmit Pre-Emphasis — Data randomization — DC-balance encoding — Receive channel deskew — Supports up to 10m CAT-5 at 1.6Gbps Integrated LVDS Terminations Built-in AT-SPEED BIST for end-to-end system testing AC-coupled interconnect for isolation and fault protection > 4KV HBM ESD protection Space-saving 64-pin TQFP package Full industrial temperature range : -40° to +85°C ■ ■ ■ ■ ■ ■ ■ ■ Applications ■ Industrial imaging (Machine-vision) and control ■ Security & Surveillance cameras and infrastructure ■ Medical imaging www.DataSheet4U.com Block Diagram 30105727 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 301057 www.national.com DS92LV3221/DS92LV3222 DS92LV3221 Pin Diagram www.DataSheet4U.com 30105730 FIGURE 1. DS92LV3221 Pin Diagram— Top View www.national.com 2 DS92LV3221/DS92LV3222 DS92LV3221 Serializer Pin Descriptions Pin # 10–8, 5–1, 64–57, 52–51, 48–44. 41–33 11 12 Pin Name TxIN[31:29], TxIN[28:24], TxIN[23:16], TxIN[15:14], TxIN[13:9], TxIN[8:0] TxCLKIN PDB I/O, Type I, LVCMOS Description Serializer Parallel Interface Data Input Pins. LVCMOS PARALLEL INTERFACE PINS I, LVCMOS I, LVCMOS Serializer Parallel Interface Clock Input Pin. Strobe edge set by R_FB configuration pin. Serializer Power Down Bar (ACTIVE LOW) PDB = L; .


DS92LV3221 DS92LV3222 XR17V352


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