H5PS1G63EFR

H5PS1G63EFR 1Gb(64Mx16) DDR2 SDRAM H5PS1G63EFR www.DataSheet4U.com This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/ Oct. 2008 1 H5PS1G63EFR Revision History Revision 0.1 Page All 5 0.2 61 0.3 0.4 1.0 64,67 56 62 56 1.1 69 History Initial data sheet released. -.500Mhz characteristics inserted. [email protected] Part Number deleted. IDD value(-25C) inserted. IDD testing parameters’ value edited. Operating temperature condition changed. IDD Value(-20L) inserted. Thermal resistance value inserted. Typo corrected. (500Mhz tWR Value) Oct. 2008 Jul. 2008 Aug. 2008 Preliminary Preliminary Date May. 2008 Remark Preliminary Jul. 2008 Preliminary Aug. 2008 Note) The H5PS1G63EFR data sheet follows all of JEDEC DDR2 standard. www.DataSheet4U.com Rev. 1.1/Oct. 2008 2 H5PS1G63EFR Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.2 Pin configuration 1.3 Pin Description 2. Functioanal Description 2.1 Simplified State Diagram 2.2 Basic Function & Operation of DDR2 SDRAM 2.2.1 Power up and Initialization 2.2.2 Programming the Mode and Extended Mode Registers 2.2.2.1 DDR2 SDRAM Mode Register Set(MRS) 2.2.2.2 DDR2 SDRAM Extended Mode Register Set 2.2.2.3 Off-Chip Driver(OCD) Impedance Adjustment 2.2.2.4 ODT(On Die Termination) 2.3 Bank Activate Command 2.4 Re...