®
LY61L1024
Rev. 2.2
128K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision Rev. 1.0 Rev. 1.1 Rev. 2.0 Rev. 2.1 Rev.2.2 Description Initial Issue Delete Icc1 Spec. Adding -10ns Spec. Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Added LL Spec. Revised Test Condition of ICC/ISB Revised FEATURES & ORDERING INFORMATION Lead free and gr...
