Document
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
μPD46128512-X
128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
Description The μPD46128512-X is a high speed, low power, 134,217,728 bits (8,388,608 words by 16 bits) CMOS Mobile Specified RAM featuring asynchronous page read and random write, synchronous burst read/write function. The μPD46128512-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
• 8,388,608 words by 16 bits organization • Asynchronous page read mode • Synchronous read and write mode • Burst length: 8 words / 16 words / continuous • Clock latency: 5, 6, 7, 8, 9, 10 • Burst sequence: Linear burst • Max clock frequency: 108/83 MHz • Byte data control: /LB (DQ0 to DQ7), /UB (DQ8 to DQ15) • Low voltage operation: 1.7 to 2.0 V • Operating ambient temperature: TA = −30 to +85 °C • Chip Enable input: /CE1 pin • Standby Mode input: CE2 pin • Standby Mode 1: Normal standby (Memory cell data hold valid) • Standby Mode 2: Density of memory cell data hold is variable
μPD46128512
Clock Asynchronous Operating supply voltage V Operating ambient temperature °C At operating mA (MAX.) (MAX.) Density of data hold 128M 32M bits -E9X
Note Note
Supply current At standby μA (TYP.) Density of data hold 0M bits 65 128M 32M bits 80 bits 16M bits 8M bits 0M bits 15
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MHz (MAX.) time ns (MAX.)
16M bits
8M bits
bits
108
70 85
1.7 to 2.0
−30 to +85
60 50 60 50
250 T.B.D. T.B.D. T.B.D.
T.B.D. T.B.D. T.B.D.
-E10X -E11X -E12X
83
70 85
Note Under consideration
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. M17507EJ2V0DS00 (2nd edition) Date Published September 2005 CP (K) Printed in Japan
The mark
shows major revised points.
2005
μ PD46128512-X
Ordering Information
μPD46128512-X is mainly shipping by wafer.
Please consult with our sales offices for package samples and ordering information.
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Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Pin Configuration
The following is pin configuration of package sample. /xxx indicates active low signal. 93-PIN TAPE FBGA (12x9)
Top View Bottom View
10 9 8 7 6 5 4 3 2 1 A BCDE FGH J K LM N P P NM L K J HGF EDCBA
Top View
A 10 9 8 7 6 5 4 3 NC NC NC NC NC NC B NC NC C NC NC NC A11 A8 /WE CLK /LB A7 NC A15 A12 A19 CE2 /ADV /UB A6 A3 A21 A13 A9 A20 /WAIT A18 A5 A2 D E F G NC A22 A14 A10 NC NC A17 A4 A1 NC H NC A16 NC DQ6 NC NC DQ1 GND A0 NC NC DQ15 DQ13 DQ4 DQ3 DQ9 /OE NC Vss DQ7 DQ12 VCC VCC DQ10 DQ0 /CE1 DQ14 DQ5 NC DQ11 DQ2 DQ8 NC NC NC NC NC NC NC NC J K L M NC NC NC N NC NC P NC
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1 NC NC
A0 to A22 /CE1 CE2 /WE /OE /LB, /UB
: Address inputs : Chip select input : Standby mode input : Write enable input : Output enable input : Byte data select input
CLK /ADV /WAIT VCC GND NC Note
: Clock input : Address Valid Input : Wait output : Power supply : Ground : No Connection
DQ0 to DQ15 : Data inputs / outputs
Note Some signals can be applied because this pin is not internally connected. Remark Refer to Package Drawing for the index mark.
Preliminary Data Sheet M17507EJ2V0DS
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μ PD46128512-X
Block Diagram
Standby mode control VCC VCCQ GND Refresh counter A0 to A22 CLK /ADV DQ0 to DQ7 DQ8 to DQ15 Address buffer Row decoder Refresh control
Memory cell array 134,217,728 bits
Address latch Sense amplifier / Switching circuit Column decoder
Input data controller
Output data controller
/WAIT
Internal state control
/CE1 CE2
/LB
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/UB /WE
/OE
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Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Truth Table Asynchronous Operation
Mode /CE1 CE2 /ADV /OE /WE /LB /UB DQ DQ0 to DQ7 DQ8 to DQ15 Not selected (Standby Mode 1) Not selected (Standby Mode 2) Word read Lower byte read Upper byte read Output disable Output disable Word write Lower byte write Upper byte write Abort write
Note2 Note1
/WAIT
H × L
H L H
× × Note3
× × L
× × H
× × L L H H
× × L H L H × L H L H
High-Z High-Z DOUT DOUT High-Z High-Z High-Z DIN DIN High-Z High-Z
High-Z High-Z DOUT High-Z DOUT High-Z High-Z DIN High-Z DIN High-Z
High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
H L
× L L H H
Notes 1. 3.
CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition). Fixed LOW or toggle HIGH → LOW → HIGH
2. If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not available.
Remark H, HIGH : VIH, L, LOW : VIL, ×: VIH or VIL Clock pin must be fixed either LOW or HIGH.
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Preliminary Data Sheet M17507EJ2V0DS
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μ PD46128512-X
Burst Operation
Mode /CE1 CE2 CLK /ADV /OE /WE /LB /UB DQ DQ0 to DQ7 Not selected (Stand.