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EDD5108AGTA-LI Dataheets PDF



Part Number EDD5108AGTA-LI
Manufacturers Elpida Memory
Logo Elpida Memory
Description 512M bits DDR SDRAM WTR
Datasheet EDD5108AGTA-LI DatasheetEDD5108AGTA-LI Datasheet (PDF)

PRELIMINARY DATA SHEET 512M bits DDR SDRAM WTR (Wide Temperature Range) EDD5108AGTA-LI (64M words × 8 bits) EDD5116AGTA-LI (32M words × 16 bits) Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL.

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PRELIMINARY DATA SHEET 512M bits DDR SDRAM WTR (Wide Temperature Range) EDD5108AGTA-LI (64M words × 8 bits) EDD5116AGTA-LI (32M words × 16 bits) Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5, 3 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period: 7.8μs • Operating ambient temperature range ⎯ TA = –40°C to +85°C www.DataSheet4U.com Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver • Data inputs, outputs, and DM are synchronized with DQS • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • ·Wide temperature range ⎯ TA = –40°C to +85°C Document No. E1304E10 (Ver. 1.0) Date Published April 2008 (K) Japan Printed in Japan URL: http://www.elpida.com ©Elpida Memory, Inc. 2008 EDD5108AGTA-LI, EDD5116AGTA-LI Ordering Information Part number EDD5108AGTA-5BLI-E EDD5108AGTA-5CLI-E EDD5108AGTA-6BLI-E EDD5108AGTA-7ALI-E EDD5108AGTA-7BLI-E EDD5116AGTA-5BLI-E EDD5116AGTA-5CLI-E EDD5116AGTA-6BLI-E EDD5116AGTA-7ALI-E EDD5116AGTA-7BLI-E Mask version G Organization (words × bits) 64M × 8 Internal banks 4 Data rate Mbps (max.) 400 333 266 32M × 16 400 333 266 JEDEC speed bin (CL-tRCD-tRP) DDR400B (3-3-3) DDR400C (3-4-4) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) DDR400B (3-3-3) DDR400C (3-4-4) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Package 66-pin Plastic TSOP (II) Part Number E D D 51 08 A G TA - 5B LI - E Elpida Memory Environment Code E: Lead Free (RoHS compliant) Spec Detail LI: WTR (−40°C to +85°C) & Low Power Speed 5B: DDR400B (3-3-3) 5C: DDR400C (3-4-4) 6B: DDR333B (2.5-3-3) 7A: DDR266A (2-3-3) 7B: DDR266B (2.5-3-3) Package TA: TSOP (II) Die Rev. Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank 51: 512M / 4-bank Organization 08: x8 16: x16 Power Supply, Interface A: 2.5V, SSTL_2 Speed Grade Compatibility www.DataSheet4U.com Speed bin DDR400B DDR400C DDR333B DDR266A DDR266B Operating Frequencies CL2 133MHz 133MHz 133MHz 133MHz 100MHz CL2.5 166MHz 166MHz 166MHz 133MHz 133MHz CL3 200MHz 200MHz 166MHz 133MHz 133MHz Preliminary Data Sheet E1304E10 (Ver. 1.0) 2 EDD5108AGTA-LI, EDD5116AGTA-LI Pin Configurations /xxx indicates active low signal. 66-pin Plastic TSOP(II) VDD VDD DQ0 DQ0 VDDQ VDDQ NC DQ1 DQ1 DQ2 VSSQ VSSQ NC DQ3 DQ2 DQ4 VDDQ VDDQ NC DQ5 DQ3 DQ6 VSSQ VSSQ NC DQ7 NC NC VDDQ VDDQ NC LDQS NC NC VDD VDD NC NC NC LDM /WE /WE /CAS /CAS /RAS /RAS /CS /CS NC NC BA0 BA0 BA1 BA1 A10(AP) A10(AP) A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS VSS DQ15 DQ7 VSSQ VSSQ DQ14 NC DQ13 DQ6 VDDQ VDDQ DQ12 NC DQ11 DQ5 VSSQ VSSQ DQ10 NC DQ9 DQ4 VDDQ VDDQ DQ8 NC NC NC VSSQ VSSQ UDQS DQS NC NC VREF VREF VSS VSS UDM DM /CK /CK CK CK CKE CKE NC NC A12 A12 A11 A11 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 VSS VSS X 16 X8 (Top view) www.DataSheet4U.com Pin name A0 to A12 BA0, BA1 DQ0 to DQ15 DQS, LDQS, UDQS /CS /RAS /CAS /WE DM, UDM, LDM Function Address inputs Bank select address Data-input/output Input and output data strobe Chip select Row address strobe Column address strobe Write enable Input mask Pin name CK /CK CKE VREF VDD VSS VDDQ VSSQ NC Function Clock input Differential Clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection Preliminary Data Sheet E1304E10 (Ver. 1.0) 3 EDD5108AGTA-LI, EDD5116AGTA-LI CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Nu.


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