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IS61NLF51236 Dataheets PDF



Part Number IS61NLF51236
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description STATE BUS SRAM
Datasheet IS61NLF51236 DatasheetIS61NLF51236 Datasheet (PDF)

IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418  256K x 72, 512K x 36 and 1M x 18 NOVEMBER 2013 18Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEATURES DESCRIPTION • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three c.

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IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418  256K x 72, 512K x 36 and 1M x 18 NOVEMBER 2013 18Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEATURES DESCRIPTION • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available • Lead-free available The 18 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence.When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency 6.5 7.5 Units 6.5 7.5 ns 7.5 8.5 ns 133 117 MHz Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. E 10/25/2013 IS61NLF25672/IS61NVF25672  IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418  BLOCK DIAGRAM x 72: A [0:17] or x 36: A [0:18] or x 18: A [0:19] ADDRESS REGISTER A2-A17 or A2-A18 or A2-A19 MODE A0-A1 BURST ADDRESS COUNTER A'0-A'1 256Kx72; 512Kx36; 1024Kx18 MEMORY ARRAY K DATA-IN REGISTER CLK CKE CONTROL LOGIC K CE CE2 CE2 } ADV WE BWŸX (X=a-h, a-d, or a,b) CONTROL REGISTER OE ZZ DQx/DQPx WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER K DATA-IN REGISTER CONTROL LOGIC 72, 36 or 18 K BUFFER 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 10/25/2013 IS61NLF25672/IS61NVF25672  IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418  Bottom View 209-Ball, 14 mm x 22 mm BGA Bottom View 165-Ball, 13 mm x 15mm BGA Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. E 10/25/2013 IS61NLF25672/IS61NVF25672  IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418  Pin Configuration ­— 256K x 72, 209-Ball PBGA (Top View) 1 2 3 4 A DQg DQg A CE2 B DQg DQg BWc BWg C DQg DQg BWh BWd D DQg DQg VSS NC E DQPg DQPc Vddq Vddq F DQc DQc VSS VSS G DQc DQc Vddq Vddq H DQc DQc VSS VSS J DQc DQc Vddq Vddq K NC NC CLK NC L DQh DQh Vd.


IS61NVF51236 IS61NLF51236 IS61NVF102418


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