Microcontrollers
MC68HC812A4
Data Sheet
M68HC12 Microcontrollers
MC68HC812A4 Rev. 7 05/2006
www.DataSheet4U.com
freescale.com
www.Da...
Description
MC68HC812A4
Data Sheet
M68HC12 Microcontrollers
MC68HC812A4 Rev. 7 05/2006
www.DataSheet4U.com
freescale.com
www.DataSheet4U.com
MC68HC812A4
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date Revision Level Description Figure 1-3. Expanded Wide Mode SRAM Expansion Schematic — Figure title changed from FLASH EEPROM to SRAM and address line designators corrected Figure 1-4. Expanded Narrow Mode SRAM Expansion Schematic — Figure title changed from FLASH EEPROM to SRAM and address line designators corrected 4 Figure 8-16. Chip-Select Control Register 0 (CSCTL0) — Corrected reset value for CSPOE (bit 5) Figure 10-1. Clock Module Block Diagram — Corrected E- and P-clock generator options Figure 11-1. PLL Block Diagram — Revised diagram to show correct placement of divide-by-two block 12.11.2 Timer Port Data Direction Register — Descriptive paragraph added for clarity Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved.
www.DataSheet4U.com
Page Number(s) 40
42
August, 2001 (Cont...
Similar Datasheet