AS5SP256K36DQ

98 97 96 95 92 91 89 87 84 99 94 93 90 88 86 85 83 DQPc DQc DQc VDDQ VSSQ 100 82 81 9.0Mb, 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect 1 2 3 4 5 6 7 8 9 A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A Austin Semiconductor, Inc. Plastic Encapsulated Microcircuit CO TS PEM COTS SSRAM AS5SP256K36DQ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 FEATURES Synchronous Operation in relation to the input Clock DQc DQc 2 Stage Registers resulting in Pipeline operation DQc DQc On chip address counter (base +3) for Burst operations VSSQ VDDQ Self-Timed Write Cycles DQc DQc On-Chip Address and Control Registers NC VDD SSRAM [SPB] Byte Write support NC VSS Global Write support DQd DQd On-Chip low power mode [powerdown] via ZZ pin VDDQ VSSQ Interleaved or Linear Burst support via Mode pin DQd DQd Three Chip Enables for ease of depth expansion without DQd DQd Data Contention. VSSQ VDDQ Two Cycle load, Single Cycle Deselect DQd DQd Asynchronous Output Enable (OE\) DQPd Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package, MS026-D/BHA Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ D...