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HY5DU121622ALT Dataheets PDF



Part Number HY5DU121622ALT
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 512Mb DDR SDRAM
Datasheet HY5DU121622ALT DatasheetHY5DU121622ALT Datasheet (PDF)

www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T 512Mb DDR SDRAM HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.0/Feb. 2003 1 www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T Revision History 1. Rev 0.0 (Feb. 19) 1) Datasheet Release in Pr.

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www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T 512Mb DDR SDRAM HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.0/Feb. 2003 1 www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T Revision History 1. Rev 0.0 (Feb. 19) 1) Datasheet Release in Preliminary version Rev. 0.0/Feb. 2003 2 www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T DESCRIPTION PRELIMINARY The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES • • • • • • • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe • • • • • • • • • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency 2 / 2.5/ 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported tRAS lock out function supported 8192 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS • • ORDERING INFORMATION Part No. HY5DU12422A(L)T-X* HY5DU12822A(L)T-X* HY5DU121622A(L)T-X* OPERATING FREQUENCY Package 400mil 66pin TSOP-II Configuration 128Mx4 64Mx8 32Mx16 Grade - D4 - D43 CL3 200MHz 200MHz Remark (CL-tRCD-tRP) DDR400 (3-4-4) DDR400 (3-3-3) * Note : D of speed indicates DDR400. Rev. 0.0 / Feb. 2003 3 www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T PIN CONFIGURATION x4 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 400mil X 875mil 66pin TSOP -II 0.65mm pin pitch ROW AND COLUMN ADDRESS TABLE ITEMS Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh 128Mx4 32M x 4 x 4banks A0 - A12 A0-A9, A11, A12 BA0, BA1 A10 8K 64Mx8 16M x 8 x 4banks A0 - A12 A0-A9, A11 BA0, BA1 A10 8K 32Mx16 8M x 16 x 4banks A0 - A12 A0-A9 BA0, BA1 A10 8K Rev. 0.0/Feb. 2003 4 www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T PIN DESCRIPTION PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, an.


HY5DU121622AT HY5DU121622ALT NTE7173


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