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STR912FAZ46 Dataheets PDF



Part Number STR912FAZ46
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description 16/32-Bit Flash MCU
Datasheet STR912FAZ46 DatasheetSTR912FAZ46 Datasheet (PDF)

www.DataSheet4U.com STR91xFAx3x STR91xFAx4x ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA Features ■ 16/32-bit 96 MHz ARM9E based MCU – ARM966E-S RISC core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) – STR91xFA implementation of core adds high-speed burst Flash memory interface, instruction prefetch queue, branch cache – Up to 96 MIPS directly from Flash memory – Single-cycle DSP instructions supported –.

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www.DataSheet4U.com STR91xFAx3x STR91xFAx4x ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA Features ■ 16/32-bit 96 MHz ARM9E based MCU – ARM966E-S RISC core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) – STR91xFA implementation of core adds high-speed burst Flash memory interface, instruction prefetch queue, branch cache – Up to 96 MIPS directly from Flash memory – Single-cycle DSP instructions supported – Binary compatible with ARM7 code Dual burst Flash memories, 32-bits wide – 256 KB/512 KB/1 MB/2 MB Main Flash – 32 KB/128 KB Secondary Flash – Sequential Burst operation up to 96 MHz – 100 K min erase cycles, 20 yr min retention SRAM, 32-bits wide – 96K bytes, optional battery backup 9 programmable DMA channels Clock, reset, and supply management – Internal oscillator operating with external 4-25 MHz crystal – Internal PLL up to 96 MHz – Real-time clock provides calendar functions, tamper, and wake-up functions – Reset Supervisor monitors supply voltage, watchdog, wake-up unit, external reset – Brown-out monitor – Run, Idle, and Sleep Mode as low as 50 uA Vectored interrupt controller (VIC) – 32 IRQ vectors, 30 interrupt pins – Branch cache minimizes interrupt latency 8-channel, 10-bit A/D converter (ADC) – 0 to 3.6 V range, 0.7 usec conversion 10 Communication interfaces – 10/100 Ethernet MAC with DMA and MII – USB Full-speed (12 Mbps) slave device ■ ■ LQFP80 12 x12mm LQFP128 14 x 14mm LFBGA144 10 x 10 x 1.7 ■ – – – – ■ CAN interface (2.0B Active) 3 16550-style UARTs with IrDA protocol 2 Fast I2C™, 400 kHz 2 channels for SPI™, SSI™, or Microwire™ ■ ■ ■ External Memory Interface (EMI) – 8- or 16-bit data, up to 24-bit addressing – Static Async modes for LQFP128 – Additional burst synchronous modes for LFBGA144 Up to 80 I/O pins (muxed with interfaces) 16-bit standard timers (TIM) – 4 timers each with 2 input capture, 2 output compare, PWM and pulse count modes 3-Phase induction motor controller (IMC) JTAG interface with boundary scan Embedded trace module (ARM ETM9) Device summary Part number STR910FAM32, STR910FAW32, STR910FAZ32, STR912FAW32 STR911FAM42, STR911FAW42, STR912FAW42, STR912FAZ42 STR911FAM44 STR911FAW44 STR912FAW44, STR912FAZ44 STR911FAM46, STR911FAW46, STR912FAW46, STR912FAZ46 STR911FAM47, STR911FAW47, STR912FAW47, STR912FAZ47 ■ ■ ■ Table 1. Reference ■ STR91xFAx32 STR91xFAx42 STR91xFAx44 STR91xFAx46 STR91xFAx47 ■ ■ May 2008 Rev 3 1/101 www.st.com 1 www.DataSheet4U.com Contents STR91xFAx3x, STR91xFAx4x Contents 1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 3.2 3.3 3.4 System-in-a-Package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARM966E-S CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4.1 3.4.2 3.4.3 Pre-Fetch Queue (PFQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Management of literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 SRAM (64K or 96K Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.1 3.5.2 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 3.7 DMA data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Non-volatile memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.1 3.7.2 Primary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 3.9 One-time-programmable (OTP) memory . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8.1 Product ID and revision level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9.1 3.9.2 3.9.3 FIQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IRQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . .


STR912FAW46 STR912FAZ46 STR911FAM47


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