STA2062A

www.DataSheet4U.com STA2062A Cartesio™ family infotainment application processor with embedded GPS Data Brief Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU (up to 333 MHz) MCU memory organization – Cache: 16 Kbyte instruction, 16 Kbyte data – 8 Kbyte instruction TCM (tightly coupled memory) – 8 Kbyte data TCM – 32 Kbyte embedded ROM for boot – Two banks of 64 Kbyte embedded SRAM – 512 Byte embedded SRAM for back-up – 4 Gbyte total linear address space – Memory extension through: Flexible static memory controller-FSMC (NOR/NAND Flash, CF/CF+, ROM, SRAM support) Mobile DDR/SDRAM controller: 16 bit data @166 MHz, 2 Chip Select, 512 Kbit each Interrupt – 64-channel interrupt controller (VIC) – 16-vectorized interrupts with 16 programmable priority level DMA – Two 8-channel double port system DMA controllers – 32 DMA request for each controller – Two external DMA requests are supported 32-channel high performance GPS correlation embedded subsystem Eight 32-bit free running timers/counters Four 16-bit extended function timer (EFT) with input capture/output compare and PWM Real-time clock (RTC) Pulse width light modulator (PWL) 32-bit watchdog timer Four autobaud UART with 64X8 transmit and 64x12 receive FIFO with DMA and hardware flow control One IrDA(SIR/MIR/FIR) interface Three I2C multi-master/slave interfaces Two synchronous serial port (SSP) with 32x32 separate transmit and receive FIFO with LFBGA361 (16x16x1.4mm) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ...