ICS548-03

www.DataSheet4U.com ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider Features Packaged in 16 pin narrow (150 mil) SOIC Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low skew (500 ps) on CLK, CLK, and CLK/2 All outputs can be tri-stated Entire chip can be powered down by changing one or two select pins 3.3V or 5.0V operating voltage Description The ICS548-03 is a low cost, low skew, high performance general-purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-2. Using our patented analog Phase-Locked Loop (PLL) techniques, the device operates from a frequency range from 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode. In applications that to need maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) mode should be used. This chip is not a zero delay buffer. Many applications may be able to use the ICS527 for zero delay dividers. Block Diagram S3:S0 4 Clock Synthesis and Divider Circuitry Output Buffer Output Buffer Output Buffer CLK CLK Clock Input Input Buffer CLK/2 OE (All outputs) MDS 548-03 1 Revision 042700 Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126 (408) 295-9800tel www.icst.com www.DataSheet4U.com ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider CLK, CLK, and CLK/2 Select Table (in MHz) S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 ...