A3S56D30ETP

A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM 256Mb DDR SDRAM Specification A3S56D30ETP A3S56D40ETP Zentel Electronics Corp. 6F-1, No. 1-1, R&D Rd. II, Hsin Chu Science Park, 300 Taiwan, R.O.C. TEL:886-3-579-9599 FAX:886-3-579-9299 Revision 2.4 Mar., 2009 A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM DESCRIPTION A3S56D30ETP is a 4-bank x 8,388,608-word x 8bit, A3S56D40ETP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The A3S56D30/40ETP achieves very high speed clock rate up to 200 MHz . FEATURES - Vdd=Vddq=2.5V+0.2V (-5E, -5, -6) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5 / 3.0 (programmable) ; Burst length - 2 / 4 / 8 (programmable) Burst type - Sequential / Interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - Support concurrent auto...