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A3S56D30ETP Dataheets PDF



Part Number A3S56D30ETP
Manufacturers Zentel
Logo Zentel
Description (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM
Datasheet A3S56D30ETP DatasheetA3S56D30ETP Datasheet (PDF)

A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM 256Mb DDR SDRAM Specification A3S56D30ETP A3S56D40ETP Zentel Electronics Corp. 6F-1, No. 1-1, R&D Rd. II, Hsin Chu Science Park, 300 Taiwan, R.O.C. TEL:886-3-579-9599 FAX:886-3-579-9299 Revision 2.4 Mar., 2009 A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM DESCRIPTION A3S56D30ETP is a 4-bank x 8,388,608-word x 8bit, A3S56D40ETP is a 4-bank x 4,194,304-word x 16bit double.

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A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM 256Mb DDR SDRAM Specification A3S56D30ETP A3S56D40ETP Zentel Electronics Corp. 6F-1, No. 1-1, R&D Rd. II, Hsin Chu Science Park, 300 Taiwan, R.O.C. TEL:886-3-579-9599 FAX:886-3-579-9299 Revision 2.4 Mar., 2009 A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM DESCRIPTION A3S56D30ETP is a 4-bank x 8,388,608-word x 8bit, A3S56D40ETP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The A3S56D30/40ETP achieves very high speed clock rate up to 200 MHz . FEATURES - Vdd=Vddq=2.5V+0.2V (-5E, -5, -6) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5 / 3.0 (programmable) ; Burst length - 2 / 4 / 8 (programmable) Burst type - Sequential / Interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - Support concurrent auto-precharge - 8192 refresh cycles / 64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9(x8) /A0-8(x16) - SSTL_2 Interface - Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch Zentel Electronics Corporation reserve the right to change products or specification without notice. Revision 2.4 Page 1/ 38 Mar., 2009 A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM Pin Assignment (Top View) 66-pin TSOP x8 x16 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD CLK, /CLK CKE /CS /RAS /CAS /WE DQ0-15 DQ0-7 UDM, LDM DM UDQS, LDQS DQS VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66pin TSOP(II) 400mil width x 875mil length 0.65mm Lead Pitch Row A0-12 Column A0-9 (x8) A0-8 (x16) : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O (x16) : Data I/O (x8) : Write Mask (x16) : Write Mask (x8) : Data Strobe (x16) : Data Strobe (x8) A0-12 BA0,1 Vdd VddQ Vss VssQ : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output Revision 2.4 Page 2/ 38 Mar., 2009 A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM PIN FUNCTION SYMBOL TYPE DESCRIPTION Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15 Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE acc.


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