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AK8815 Dataheets PDF



Part Number AK8815
Manufacturers Asahi Kasei Microsystems
Logo Asahi Kasei Microsystems
Description (AK8815 / AK8816) NTSC/PAL Digital Video Encoder
Datasheet AK8815 DatasheetAK8815 Datasheet (PDF)

ASAHI KASEI [AK8815/16] www.DataSheet4U.com AK8815/16 NTSC/PAL Digital Video Encoder GENERAL DESCRIPTION The AK8815/16 is a digital video encoder which is developed for portable apparatus applications such as cellular phone etc.. ITU-R BT.601 level compatible Y, Cb,and Cr signals which correspond to square pixel are encoded into either NTSC or PAL compatible composite video signal. Interface is made in HSYNC-, VSYNC- synchronized slave-mode operation. It is controlled via a 4-wire serial inter.

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ASAHI KASEI [AK8815/16] www.DataSheet4U.com AK8815/16 NTSC/PAL Digital Video Encoder GENERAL DESCRIPTION The AK8815/16 is a digital video encoder which is developed for portable apparatus applications such as cellular phone etc.. ITU-R BT.601 level compatible Y, Cb,and Cr signals which correspond to square pixel are encoded into either NTSC or PAL compatible composite video signal. Interface is made in HSYNC-, VSYNC- synchronized slave-mode operation. It is controlled via a 4-wire serial interface. FEATURES • • • • • • • • • • • • • • • • • • • • NTSC-M, PAL-B, D, G, H, I encoding Composite Video Output Y:Cb:Cr 4:2:2 Square Pixel Data Input H/V Slave Operation Y filtering: 2 x over-sampling C filtering: 4 x over-sampling 9-bit DAC Macrovision Copy Protection Rev. 7.1 * (only AK8815 ) VBID ( CGMS-A ) Compatible WSS Compatible On-chip Quartz Crystal Oscillator circuit Clock: Square Pixel data rate 24.5454 MHz ( NTSC ), 29.50 MHz ( PAL ) Device Control I / F : 4- wire Serial Bus Interface On-chip Color Bar Output Black Burst Output Internal Operating Voltage: 2.7 V ~ 3.3 V supplying Interface Power Supply ( 1.6 V ~ 2.0 V or 2.7 V ~ 3.3 V ) Power-down function Monolithic CMOS 57 pin FBGA ( 5 mm sq ) ( lead-free package ) (*Note) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in written by Macrovision. Reverse engineering or disassembly is prohibited. MS0331-E-00 1 2004 / 08 ASAHI KASEI [AK8815/16] www.DataSheet4U.com BLOCK DIAGRAM XTI/CLKIN XTO CLKINV RSTN PDN CS SCLK SDI SDO VREF CLKMD CLK Generator u-p I/F Register Timing Controller VREF Generator IREF VSYNC HSYNC D[7:0] Synchronization Control SYNC Generator Y Cb Cr U Cos SubCarrier Generator Sin V C Chroma LPF Filter (x 2 Interpolator) TEST Logic TEST ATPG UD[4:0] VBID & WSS Macrovision Input Data Control Y LPF Filter (x 2 Interpolator) 9-bit DAC VIDEOOUT CLKOUT Cb/Cr LPF Filter (x 2 Interpolator) Color Bar & Background Color Control PVDD2 PVSS2 PVDD1 PVSS1 DVDD DVSS XVDD AVDD AVSS MS0331-E-00 2 2004 / 08 ASAHI KASEI [AK8815/16] www.DataSheet4U.com ORDERING GUIDE AK8815/16VG 57 pin FBGA PIN LAYOUT 57pin FBGA 9 8 7 6 5 4 3 2 1 A B C D E F G H J Bottom View MS0331-E-00 3 2004 / 08 ASAHI KASEI [AK8815/16] www.DataSheet4U.com PIN FUNCTIONAL DESCRIPTION (preliminary) No. Pin Name I/O Function Quartz crystal resonator connection pin ( to be grounded via a 18 pF capacitor as shown in the recommended circuit ). NTSC: 24.5454 MHz / PAL: 29.50 MHz Hi-Z input is acceptable to this pin at PDN = L. Input from an external crystal oscillator should be connected to this pin. Quartz crystal resonator connection pin ( to be grounded via a 22 pF capacitor as shown in the recommended circuit ). NTSC: 25.5454 MHz / PAL: 29.50 MHz DVSS level is output on this pin at PDN = L. Clock Mode setting pin. Should be connected to either DVDD or DGND. GND connection: when a crystal resonator is used XVDD connection: when an external crystal oscillator is used Clock output pin. NTSC: 24.5454 MHz / PAL: 29.50 MHz This becomes Hi-Z output at PDN =L. “L “ : data is latched with rising edge. “H” : data is latched with falling edge. Internal clock is inverted (internal operation timing edge is inverted. CLKOUT is not affected). Connect to either DVDD or DGND. Power Down Pin. After returning from PD mode to normal operation, RESET Sequence should be done to AK8815/16. “L “(GND level): Power-down “H “: normal operation Reset input pin. In order to initialize the device , an initialization must be made in accordance with the reset sequence. “L “ : reset “H “ : reset Hi-Z input is acceptable to this pin at PDN = L. Serial Data clock input pin. 15 MHz ( max ) Hi-Z input is acceptable to this pin at PDN = L. Serial Data input pin. Hi-Z input is acceptable to this pin at PDN = L. Serial Data output pin. This becomes high output at PDN = L. This pin interfaces one-to-one with a controller through a dedicated pin. Serial Data Chip Enable signal input pin. This pin interfaces one-to-one with a controller through a dedicated pin. L : disabled condition ( un-selected ) H : enabled condition ( selected ) Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin (MSB). Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. D.


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