Document
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ASAHIKASEI
[AK8813/14]
AK8813/14
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The AK8813/14 is low voltage, low power and small packaged Digital Video Encoder. It is suitable for a STB or Digital TV. It converts ITU-R.BT601/656 standard 8- bit parallel data into analog composite video signal, S-video in NTSC and PAL formats. AK8813/14 supports Copy protection, Closed Captioning and Video Blanking ID(CGMS-A) and WSS. These functions are controlled by high-speed I2C Bus interface.
FEATURES
• NTSC-M, PAL-B,D,G,H,I,M,N encoding. • Simultaneous composite video signal and S-video signal outputs • ITU-R BT.656 4:2:2 8-bit Parallel Input - EAV Decoding • Master/Slave Operation - Digital Field Sync I/O - Digital Vertical/Horizontal Sync I/O • Y filtering • C filtering • Triple 10-bit DACs • I2C Bus Interface (400kHz) • Closed Caption encoding (NTSC: line 21,284-SMPTE PAL: line 22,335-CCIR) • Macrovision Copy Protection Rev. 7.1 * (only AK8814 ) • VBID, CGMS-A(EIAJ CPR-1024) • WSS • On-chip color bar generator • Low power consumption • 2.8V to 3.3V operation CMOS Monolithic • 48pin LQFP Package / 57pin FBGA Package
(*Note) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in written by Macrovision. Reverse engineering or disassembly is prohibited.
2 x over-sampling 4 x over-sampling
• Single 27MHz Clock (The polarity could be inverted by SYSINV pin)
Rev.00
-1-
2004/Oct
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ASAHIKASEI
[AK8813/14]
Block Diagram
SELA SCL SDA CLKNV CLK HSYNC VSYNC/PD /RESET
VREFOUT VREFIN
u-P I/F (I C) & Register
2
Timing Generator
Macrovision
CGMS-A WSS
VREF Generator
IREF
Sync-Form Generator
Luma Filter (x 2 Interpolator) Input Formatter EAV Decode
Y Delay
10-bit DAC
Y
Data[7:0]
10-bit DAC Chroma LPF Filter (x 2 Interpolator)
Composite
4:2:2 to 4:4:4 (x 2 Interpolator)
Sub-Carrier Generator
C Delay
10-bit DAC
C
DVDD DVSS
AVDD AVSS
Rev.00
-3-
2004/Oct
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ASAHIKASEI
[AK8813/14]
ORDERING GUIDE
AK8813VQ: LQFP48 Non-Macrovision (Pb Free) AK8813VG: FBGA57 Non-Macrovision AK8813VGP: FBGA57 Non-Macrovision (Pb Free) AK8814VQ: LQFP48 Macrovision (Pb Free) AK8814VG: FBGA57 Macrovision (Pb Free)
Rev.00
-4-
2004/Oct
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ASAHIKASEI
[AK8813/14]
PIN LAYOUT
48pin LQFP
VREFOUT VREFIN DVDD AVDD DVSS
AVSS
IREF
UD4
UD5 UD6 UD7 DVSS SYSCLK DVDD UD8 DVDD FID/VSYNC HSYNC DVSS SYSINV
37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12
UD3 D7
UD2 D6
UD1
UD0
CVBS AVSS C AVDD Y AVSS /RESET PD SDA SCL SELA TEST
UD9
D5
D4
DVDD
DVSS
D3
D2
D1
D0
TEST
57pin FBGA
9 8 7 6 5 4 3 2 1 A B C D E F G H J
Bottom View Rev.00 -52004/Oct
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ASAHIKASEI
[AK8813/14]
PIN/FUNCTION 48pin LQFP
No.
1 2-5, 8-11 12-13 14 15 16 17
Pin Name
UD9 D7 - D0 TEST SELA SCL SDA PD
I/O
I/O I I I I I/O I
Description
Test pin. Open for normal operation 27MHz 8-Bit 4:2:2 multiplexed Y,Cb,Cr Data Input. For Rec.656 format, AK8813/14 decodes EAV. For non-Rec.656 format (without EAV), AK8813/14 operates in Master or Slave mode. Test pin. Ground for normal operation The slave address is set with this pin. “L”:40H “H”:42H Serial interface clock Serial interface data Power Down Pin. After returning from PD mode to normal operation, RESET Sequence should be done to AK8813/14. After this pin becomes “L”, AK8813/14 starts the internal initializing sequence. After initializing sequence, AK8813/14 is set NTSC mode, Rec.656 decoding mode. All DACs Off condition. After power up, AK8813/14 must be initialized with this pin. (27MHz Clock is necessary for reset sequence.) Output of Luminance Signal. Output of the Chrominance signal Output of Composite Video signal Output of the Internal Vref. Terminate with 0.1uF or more capacitor. Input of the Reference Voltage The currents flow this pin adjusts the full-scale output current of the DAC. Connect this pin to Analog ground via a 6.8kohm resistor ( better than +/1% accuracy ). Test pin. Open for normal operation 27MHz Clock Input. The polarity could be inverted by SYSINV. Test pin. Open for normal operation Either of FID or VSYNC selected by the register. Rec.656 decode mode :Output Master mode : Output Slave mode : Input FID shows that “L” is odd field and ”H” is even field. Rec.656 decode mode : Output Master mode : Output Slave mode : Input “L “ : data is latched with rising edge. “H” : data is latched with falling edge. Analog Power Supply Digital Power Supply Analog Ground Digital Ground
18
/RESET
I
20 22 24 27 28 29 32-39 41 43
Y C COMPOSITE VREFOUT VREFIN IREF UD0-UD7 SYSCLK UD8 FID /VSYNC
O O O O I O I/O I I/O
45
I/O
46 48 21,26 6,31, 42,44 19,23.