PO74HSTL314A

www.DataSheet4U.com PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 07/28/06 FEATURES: . Patented Technology . Four HSTL differential outputs . The two pair of LVDS/LVPECL/HSTL/ differential or single-ended inputs . Hot-swappable/-insertable . Operating frequency up to 500MHz with 2pf load . Operating frequency up to 480MHz with 5pf load . Operating frequency up to 400MHz with 15pf load . Very low output pin to pin skew < 80ps . Very low pulse skew < 80ps . 2.8-ns propagation delay (typical) . 2.4V to 3.6V power supply . Industrial temperature range: –40°C to 85°C . 20-pin 209 mil SSOP package DESCRIPTION: The PO74HSTL314 is a low-skew, 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on 0.35um CMOS technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 500MHz . The device features two differential input paths that are multiplexed plexed internally. This mux is controlled by the CLK_SEL pin. The PO74HSTL314 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL or LVCMOS / LVTTL single-ended signal to four HSTL differential loads. Since the PO74HSTL314 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-...