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FDS4897C Dataheets PDF



Part Number FDS4897C
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual N & P-Channel PowerTrench MOSFET
Datasheet FDS4897C DatasheetFDS4897C Datasheet (PDF)

FDS4897C Dual N & P-Channel PowerTrench® MOSFET November 2005 FDS4897C Dual N & P-Channel PowerTrench® MOSFET General Description These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance. Application • Inverter • Power Supplies Features • Q1: N-Channel 6.2A, 40V RDS(on) = 29mΩ @ VGS = .

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FDS4897C Dual N & P-Channel PowerTrench® MOSFET November 2005 FDS4897C Dual N & P-Channel PowerTrench® MOSFET General Description These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance. Application • Inverter • Power Supplies Features • Q1: N-Channel 6.2A, 40V RDS(on) = 29mΩ @ VGS = 10V RDS(on) = 36mΩ @ VGS = 4.5V • Q2: P-Channel –4.4A, –40V RDS(on) = 46mΩ @ VGS = –10V RDS(on) = 63mΩ @ VGS = –4.5V • High power handling capability in a widely used surface mount package • RoHS compliant DD2 DD2 DD1 DD1 SO-8 Pin 1 SO-8 G2 S2 G G1 S1 S S S Q2 5 4 6 3 Q1 7 2 8 1 Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note 1a) (Note 1a) (Note 1b) (Note 1c) TJ, TSTG Operating and Storage Junction Temperature Range Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) Package Marking and Ordering Information Device Marking Device Reel Size FDS4897C FDS4897C 13” ©2005 Fairchild Semiconductor Corporation FDS4897C Rev C(W) Q1 Q2 40 40 ±20 ±20 6.2 –4.4 20 –20 2 1.6 1 0.9 –55 to +150 Units V V A W °C 78 40 Tape width 12mm °C/W °C/W Quantity 2500 units www.fairchildsemi.com FDS4897C Dual N & P-Channel PowerTrench® MOSFET Electrical Characteristics Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Type Min Typ Max Units Drain-Source Avalanche Ratings (Note 3) EAS Drain-Source Avalanche VDD = 40 V, ID = 7.3 A, L = 1 mH Q1 Energy (Single Pulse) VDD = –40 V, ID =–8.7 A, L = 1 mH Q2 IAS Drain-Source Avalanche Q1 Current Q2 Off Characteristics BVDSS Drain-Source Breakdown Voltage ΔBVDSS ΔTJ IDSS IGSS Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage VGS = 0 V, ID = 250 μA Q1 VGS = 0 V, ID = –250 μA Q2 ID = 250 μA, Referenced to 25°C Q1 ID = –250 µA, Referenced to 25°C Q2 VDS = 32 V, VGS = 0 V Q1 VDS = –32 V, VGS = 0 V Q2 VGS = ±20 V, VDS = 0 V All On Characteristics (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 μA Q1 VDS = VGS, ID = –250 µA Q2 ΔVGS(th) Gate Threshold Voltage ID = 250 μA, Referenced to 25°C Q1 ΔTJ Temperature Coefficient ID = –250 µA, Referenced to 25°C Q2 RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 6.2 A Q1 VGS = 4.5 V, ID = 4.8 A VGS = 10 V, ID = 6.2 A, TJ = 125°C VGS = –10 V, ID = –4.4 A Q2 VGS = –4.5 V, ID = –3.8 A VGS = –10 V, ID = –4.4 A, TJ = 125°C gFS Forward Transconductance VDS = 10 V, ID = 6.2 A Q1 VDS = –10 V, ID =–4.4 A Q2 Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Resistance Q1 Q1 VDS = 20 V, VGS = 0 V, f = 1.0 MHz Q2 Q1 Q2 Q2 VDS = –20 V, VGS = 0 V, f = 1.0 MHz Q1 Q2 f = 1.0 MHz Q1 Q2 27 mJ 38 mJ 7.3 A –8.7 40 V –40 34 mV/°C –40 1 μA –1 ±100 nA 1 1.9 3 V –1 –1.7 –3 –5 mV/°C 4 21 29 mΩ 26 36 29 43 37 46 50 63 55 73 21 S 12 760 pF 1050 100 pF 140 60 pF 70 1.2 Ω 9 FDS4897C Rev C(W) www.fairchildsemi.com FDS4897C Dual N & P-Channel PowerTrench® MOSFET Electrical Characteristics (continued) TA = 25°C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Switching Characteristics (Note 2) td(on) Turn-On Delay Time Q1 Q1 VDD = 20 V, ID = 1 A, Q2 tr Turn-On Rise Time VGS = 10V, RGEN = 6 Ω Q1 Q2 td(off) Turn-Off Delay Time Q2 Q1 VDD = –20 V, ID = –1 A, Q2 tf Turn-Off Fall Time VGS = –10V, RGEN = 6 Ω Q1 Q2 Qg Total Gate Charge Q1 Q1 VDS = 20 V, ID = 6.2 A, VGS = 10 V Q2 Qgs Gate-Source Charge Qgd Gate-Drain Charge Q1 Q2 Q2 VDS = –20 V, ID = –4.4 A,VGS =–10 V Q1 Q2 Drain–Source Diode Characteristics VSD Drain-Source Diode Forward VGS = 0 V, IS = 1.3 A (Note 2) Q1 Voltage VGS = 0 V, IS = –1.3 A (Note 2) Q2 trr Diode Reverse Recovery Q1 Q1 Time IF = 6.2 A, diF/dt = 100 A/µs Q2 Qrr Diode Reverse Recovery Q2 Q1 Charge IF = –4.4 A, diF/dt = 100 A/µs Q2 9 18 ns 12 22 5 10 ns 15 27 23 37 ns 45 72 3 6 ns 18 32 14 20 nC 20 28 2.4 nC 3 2.8 nC 4 0.7 1.2 V –0.7 –1.2 17 ns 24 7 nC 12 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the use.


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