CYM1465A

65A www.DataSheet4U.com CYM1465A 512K x 8 PDIP Static RAM Features 4.5V–5.5V operation CMOS SRAM for optimum speed and power Low active power (165 mW max.) Low standby power (L Version)—(110 µW max) 2V data retention (L Version) JEDEC-compatible pinout 32-pin, 0.6-inch-wide DIP package TTL-compatible inputs and outputs an automatic power-down feature that reduces power consumption by more than 99% when deselected. Writing to the SRAM is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input/output pins (I/O0 through I/O7) of the device is then written into the memory location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip select (CE) and output enable (OE) LOW while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins (A0 through A18) will appear on the eight appropriate data input/output pins (I/O0 through I/O7).The eight input/output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CYM1465A is available in a 32-pin 600-mil wide body PDIP package. Functional Description The CYM1465A is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an acti...