AS7C31026A

January 2001 Advance www.D a t a S h e e t 4Information U.com ® AS7C1026A AS7C31026A 5V/3.3V 64K X 16 CMOS SRAM Features AS7C1026A (5V version) AS7C31026A (3.3V version) Industrial and commercial versions Organization: 65,536 words × 16 bits Center power and ground pins for low noise High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time Latest 6T 0.25u CMOS technology 2.0V data retention Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin 400 mil TSOP II - 48-ball 6 mm × 8 mm CSP mBGA Low power consumption: ACTIVE - 660 mW (AS7C1026A) / max @ 10 ns - 324 mW (AS7C31026A) / max @ 10 ns ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA Low power consumption: STANDBY - 55 mW (AS7C1026A) / max CMOS I/O - 36 mW (AS7C31026A) / max CMOS I/O Logic block diagram A0 A2 A3 A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 Pin arrangement 44-Pin SOJ, TSOP II (400 mil) VCC A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 48-CSP mini Ball-Grid-Array Package Row decoder A1 64K × 16 Array GND I/O buffer Control circuit Column decoder A8 A9 A10 A11 A12 A13 A14 A15 WE 1 2 3 OE A0 A LB B I/O8 UB A3 C I/O9 ...