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LF43891 Dataheets PDF



Part Number LF43891
Manufacturers LOGIC Devices Incorporated
Logo LOGIC Devices Incorporated
Description 9 x 9-bit Digital Filter
Datasheet LF43891 DatasheetLF43891 Datasheet (PDF)

LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter DESCRIPTION The LF43891 is a video-speed digital filter that contains eight filter cells (taps) cascaded internally and a shiftand-add output stage. A 9 x 9 multiplier, three decimation registers, and a 26-bit accumulator are contained in each filter cell. The output stage of the LF43891 contains a 26-bit accumulator which can add the contents of any filter stage to the output stage ac.

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LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter DESCRIPTION The LF43891 is a video-speed digital filter that contains eight filter cells (taps) cascaded internally and a shiftand-add output stage. A 9 x 9 multiplier, three decimation registers, and a 26-bit accumulator are contained in each filter cell. The output stage of the LF43891 contains a 26-bit accumulator which can add the contents of any filter stage to the output stage accumulator shifted right by 8 bits. 8-bit unsigned or 9-bit two’s complement format for data and coefficients can be independently selected. Expanded coefficients and word sizes can be processed by cascading multiple LF43891s to implement larger filter lengths without affecting the sample rate. By reducing the sample rate, a single LF43891 can process larger filter lengths by using multiple passes. The sampling rate can range from 0 to 40 MHz. Over 1000 taps may be processed without overflows due to the architecture of the device. The output sample rate can be reduced to one-half, one-third, or onefourth the input sample rate by using the three decimation registers contained in every filter cell. Matrix multiplication, N x N spatial correlations/convolutions, and other 2-D operations for image processing can also be achieved using these registers. FEATURES u u u u 30 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or 9-bit Two’s Complement Data/Coefficients u 26-bit Data Outputs u Shift-and-Add Output Stage for Combining Filter Outputs u Expandable Data Size, Coefficient Size, and Filter Length u User-Selectable 2:1, 3:1, or 4:1 Decimation u Replaces Harris HSP43891 u 84-pin PLCC, J-Lead LF43891 BLOCK DIAGRAM DIN8-0 9 DIENB, CIENB, ERASE, DCM1-0 5 CIN8-0 9 FILTER CELL 0 9 FILTER CELL 1 9 FILTER CELL 2 9 FILTER CELL 3 9 FILTER CELL 4 9 FILTER CELL 5 9 FILTER CELL 6 9 FILTER CELL 7 9 COUT8-0 ADR2-0 3 26 26 26 26 26 26 26 26 COENB MUX 26 SHADD SENBL SENBH RESET 26 OUTPUT STAGE TO ALL CELLS CLK TO ALL REGISTERS SUM25-0 Video Imaging Products 1 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter FIGURE 1. FILTER CELL DIAGRAM CIENB.D DCM0.D DCM1.D LD CIN8-0 C REG C8-0 LD D1 REG 1 MUX LD D2 REG LD D3 REG 1 MUX TRI-STATE BUFFER ON FILTER CELL 7 ONLY COUT8-0 COENB 0 D8-0 0 C8-0 DIENB.D LD DIN8-0 X REG X8-0 M REG0 DCM1 DCM0 RESET DIENB CIENB ADR0 ADR1 ADR2 ERASE LATCHES DCM1.D DCM0.D RESET.D DIENB.D CIENB.D ADR0.D ADR1.D ADR2.D ERASE.D RESET.D ERASE.D ACCUMULATOR ACC25-0 SIGN EXTENSION 25-18 17-0 M REG1 CELL n CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 ACC.D25-0 ADR0 ADR1 ADR2 DECODER CELL n D Q LD T REG AOUT25-0 CLK RESET.D TO ALL REGISTERS TO ALL REGISTERS (EXCEPT ACCUMULATOR AND T-REGISTER) Video Imaging Products 2 08/16/2000–LDS.43891-J LF43891 DEVICES INCORPORATED 9 x 9-bit Digital Filter FIGURE 2. OUTPUT STAGE DIAGRAM SHADD ADR2-0.D 26 26 26 26 26 26 26 26 FILTER CELL DESCRIPTION 9-bit coefficients are loaded into the C register (CIN8-0 ) and are output as COUT8-0 (the COENB signal enables the COUT8-0 outputs). The path taken by the coefficients varies according to the decimation mode chosen. With no decimation, the coefficients move directly from the C register, bypassing all decimation registers, and are available at the output on the following clock cycle. When decimation is chosen, the coefficient output is delayed by 1, 2, or 3 clock cycles depending on how many decimation registers the coefficients pass through (D1, D2, or D3). The number of decimation registers the coefficients pass through is determined by DCM1-0 . Refer to Table 1 for choosing a decimation mode. CIENB enables the C and D registers for coefficient loading. The registers are loaded on the rising edge of CLK when CIENB is LOW. CIENB is latched and delayed internally which enables the registers for loading one clock cycle after CIENB goes active (loading takes place on the second rising edge of CLK after CIENB goes LOW). Therefore, CIENB must be LOW one clock cycle before the coefficients are placed on the CIN8-0 inputs. The coefficients are held when CIENB is HIGH. DIENB enables the X register for the loading of data. The X register is loaded on the rising edge of CLK when DIENB is LOW. DIENB is latched and delayed internally (loading takes place on the second rising edge of CLK after DIENB goes LOW). Therefore, DIENB must be LOW one clock cycle before the data is placed on the DIN8-0 inputs. The X register is loaded with all zeros when DIENB is HIGH. The output of the C register (C8-0) and X register (X8-0) provide the inputs of the 9 x 9 multiplier. The multiplier is followed by two pipeline registers, D CELL RESULT MUX Q 26 0 18 ZERO MUX SIGN EXTENSION 25-18 17-0 17-0 1 0 26 OUTPUT BUFFER 25-8 26 1 OUTPUT MUX 26 0 D Q SENBL SENBH 2 TRI-STATE BUFFER 26 CLK RESET.D TO ALL REGISTERS TO ALL REG.


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