DS3647A

www.DataSheet4U.com DS3647A Quad TRI-STATE MOS Memory I O Register February 1986 DS3647A Quad TRI-STATE MOS Memory I O Register General Description The DS3647A is a 4-bit I O buffer register intended for use in MOS memory systems This circuit employs a fall-through latch for data storage This method of latching captures the data in parallel with the output thus eliminating the delays encountered in other designs This circuit uses Schottkyclamped transistor logic for minimum propagation delay and employs PNP input transistors so that input currents are low allowing a large fan-out for this circuit which is needed in a memory system Two pins per bit are provided and data transfer is bi-directional so that the register can handle both input and output data The direction of data flow is controlled through the input enables The latch control when taken low will cause the register to hold the data present at that time and display it at the outputs Data can be latched into the register independent of the output disables or EXPANSION input Either or both of the outputs may be taken to the high-impedance state with the output disables The EXPANSION pin disables both outputs to facilitate multiplexing with other I O registers on the same data lines The DS3647A features TRI-STATE outputs The ‘‘B’’ port outputs are designed for use in bus organized data transmission systems and can sink 80 mA and source b5 2 mA Data going from port ‘‘A’’ to port ‘‘B’’ and from ‘‘B’’ to port ‘‘A’’ is i...